Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

836

Datasheet

Pipe A Gamma Correction Max Red

Default: 00010000h

7:5

0b

RW

[DevCTG, DevCDV, DevVLVP]: This field selects the number of bits 

per color sent to a receiver device connected to this port. Color format takes place on 

the Vblank after being written. Color format change can be done independent of a pixel 

clock change in DisplayPort. 

Selecting a pixel color depth higher or lower than the pixel color depth of the frame 

buffer results in dithering the output stream. 

For further details on Display Port fixed frequency programming to accommodate these 

formats refer to DP Frequency Programming in DPLL section of Bspec. 

000 = 8 bits per color (Default) 

001 = 10 bits per color 

010 = 6 bits per color  

011 = RESERVED 

1xx = RESERVED

4

0b

RW

[DevCTG, DevCDV]: This bit enables dithering for DisplayPort 

6bpc or 8bpc modes 

0 Dithering disabled (Default) 

1 Dithering enabled  

Programming note: Dithering should only be enabled for 8 bpc or 6 bpc.

3:2

0b

RW

[DevCTG, DevCDV]: This bit selects dithering type for DisplayPort 

6bpc or 8bpc modes 

00 - Spatial only (default) 

01- Spatio-Temporal 1 

10- Spatio-Temporal 2 (testmode) 

11- Temporal only (testmode)

1

0b

RW

[DevCTG, DevCDV]: 

0 Do not reset DDA 

1 Reset DDA every 8th display frame

0

0b

RW

Write as zero

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h