Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Power Management
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
85
6.2.2
System States
 shows the transitions rules among the various states. Note that transitions 
among the various states may appear to temporarily transition through intermediate 
states. These intermediate transitions and states are not listed in the table.
Table 49. General Power States for System 
States/Sub-
states
Legacy Name / Description
G0/S0/C0
FULL ON: CPU operating. Individual devices may be shut down to save 
power. The different CPU operating levels are defined by Cx states.
G0/S0/Cx
Cx State: CPU manages C-state itself.
G1/S3
Suspend-To-RAM(STR): The system context is maintained in system 
DRAM, but power is shut to non-critical circuits. Memory is retained, and 
refreshes continue. All external clocks are shut off; RTC clock and internal 
ring oscillator clocks are still toggling.
G1/S4
Suspend-To-Disk (STD): The context of the system is maintained on the 
disk. All of the power is shut down except power for the logic to resume.
The S4 and S5 states are treated the same.
G2/S5
Soft-Off: System context is not maintained. All of the power is shut down 
except power for the logic to restart. A full boot is required to restart. A full 
boot is required when waking.
The S4 and S5 states are treated the same.
SoC G3
SoC Mechanical OFF. System context is not maintained. All power to the 
SoC is shutdown except for the RTC. All of the power to the rest of the 
system is shut down except power for the logic to restart. No SoC “Wake” 
events are possible, because the SoC does not have any power. when SoC 
power returns, transition will depend on the state just prior to the entry to 
SoC G3.
G3
Mechanical OFF. System is not maintained. All power shutdown except for 
the RTC. No “Wake” events are possible, because the system does not have 
any power. This state occurs if the user removes the batteries, turns off a 
mechanical switch, or if the system power supply is at a level that is 
insufficient to power the “waking” logic. When system power returns, 
transition will depend on the state just prior to the entry to G3.
Table 50. ACPI PM State Transition Rules (Sheet 1 of 2)
Present 
State
Transition Trigger
Next State
G0/S0/C0
IA Code MWAIT or LVL Rd
C0/S0/Cx
PM1_CNT.SLP_EN bit set
G1/Sx or G2/S5 state (specified by 
PM1_CNT.SLP_TYP)
Power Button Override
G2/S5
Mechanical Off/Power Failure
G3