Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

857

Display Arbitration Control 2

Default: 00001111h

15

0b

RW

[DevVLVP]  

1 use 64 as precision multipler to increase precision to be stored in 7-bit Sprite C drain 

latency value 

0 use 32 as precision multipler to increase percision to be stored in 7-bit Sprite C drain 

latency value

14:8

0b

RW

[DevVLVP]

7

0b

RW

[DevVLVP] 

1 use 64 as precision multipler to increase precision to be stored in 7-bit Plane B drain 

latency value 

0 use 32 as precision multipler to increase percision to be stored in 7-bit Plane B drain 

latency value

6:0

0b

RW

[DevVLVP]

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

RE

SERV

ED

SPRITE_D_ST

A

R

T

_HIGH_ORDER

RE

SE

RVED

_

1

SP

RITE

_CS

TAR

T_HIG

H

_O

RDER

RE

SERV

ED_MBZ

SPRITE_B_ST

A

R

T

_HIGH_ORDER

RE

SE

RVED_MBZ

_

1

SPRITE_A_ST

A

R

T

_HIGH_ORDER

31:13

0b

RW

Reserved.

12

1b

RW

This field is the high order bits for Sprite D Start 

pointer. Combinbed with lower order 8-bit Sprite D Start pointer, this field selects the 

end of the ram used for Sprite C and the start of the RAM for Sprite D. If sprite C is 

unused, this field can be set to the same value as Sprite C START. If Sprite D is unused, 

this field can be set to TOTALSIZE-1. It must be programmed to a number greater than 

or equal to the value in Sprite C START and less than the total size of the RAM 

(TOTALSIZE). The size of the Sprite C FIFO will be (Sprite D START-Sprite C START)*64. 

The size of the Sprite D FIFO will be (TOTALSIZE-Sprite D START-1) *64 bytes. 

[DevBLC and DevCTG]: Reserved: Write as zero.