Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
861
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
DISPLA
Y_FIFO_S
ELF_RE
FRESH_W
A
TE
RMARK
1_HIGH_OR
DER_PROGRAMMING
RESE
RVED
_1
SPRITE
_D_FIFO_W
A
TER
M
ARK1_HIGH_
ORDER
RESE
RVED
_2
SPRITE_C_FIFO_W
A
TER
M
ARK1_HIGH_
ORDER
RESE
RVED
_3
DISPLA
Y_PLAN
E
_
B_FIFO_W
A
T
ER
M
A
RK1_HIGH_
ORDER
RESE
RVED
_4
SPRITE
_B_FIFO_W
A
TER
M
ARK1_HIGH_
ORDER
RESE
RVED
_5
SPRITE
_A_FIFO_W
A
TER
M
ARK1_HIGH_
ORDER
RESE
RVED
_6
DISP
LA
Y_P
LANE
_
A_FIFO_W
A
T
ER
MA
RK1_HIG
H
_
O
R
DER
Bit
Range
Default &
Access
Field Name (ID): Description
31:25
0b
RW
RESERVED:
Reserved.
24
0b
RW
DISPLAY_FIFO_SELF_REFRESH_WATERMARK1_HIGH_ORDER_PROGRAMMING
:
This field is the high order bit for the SR WM1 pointer . Combined with the lower order
9-bit SR FIFO WM1 pointer, it forms a 10-bit SR FIFO WM1 pointer. This register defines
the value of the watermark used by the Display streamer in case the CPU is in C2/C3/C4
and the memory has entered self refresh. Number in 64Bs of space in FIFO above which
the Display Stream will generate requests to Memory (Value should be as recommended
in the high priority bandwidth analysis spreadsheet).Note [DevCL, DevCTG, DevCDV]:
When calculating watermark values for 15/16bpp display formats, assume 32bpp for
purposes of calculation using the high priority bandwidth analysis spreadsheet.
23:21
0b
RW
RESERVED_1:
Reserved.
20
0b
RW
SPRITE_D_FIFO_WATERMARK1_HIGH_ORDER:
This field is the high order bit for
Sprite D FIFO WM1. Combined with lower order 8-bit Sprite D FIFO WM1, it forms a 9-
bit Sprite D FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display
A Stream will generate requests to Memory (Value should be as recommended in the
high priority bandwidth analysis spreadsheet).
19:17
0b
RW
RESERVED_2:
Reserved.
16
0b
RW
SPRITE_C_FIFO_WATERMARK1_HIGH_ORDER:
This field is the high order bit for
Sprite C FIFO WM1. Combined with lower order 8-bit Sprite C FIFO WM1, it forms a 9-bit
Sprite C FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display A
Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).