Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

867

Cursor A Base Address Register

Default: 00000000h

31:30

0b

RW

Write as zero.

29:28

0b

RW

[DevBW, DevCL, DevCDV] A state machine handles the synchronization 

of the switch to both vertical blank signals. So as far as the software is concerned, when 

both display pipes are being used, it can be switched at any time; the hardware will 

synchronize the switch.  

00 = HW cursor is attached to Display Pipe A. This is the default after reset. 01 = HW 

cursor is attached to Display Pipe B. 

10 = Reserved for pipe C 

11 = Reserved for pipe D 

[DevBLC] and [DevCTG] Reserved: Write as zero.

27

0b

RW

. This bit should be turned on when using Cursor A as a 

popup cursor. When in popup mode, hardware interprets the cursor base address as a 

physical address instead of a graphics address.0 = Cursor A is hi-res 

1 = Cursor A is popup

26

0b

RW

This bit only has an effect when using the cursor in a 

non-VGA mode. In VGA pop-up operation, the cursor data will always bypass the 

gamma (palette) unit. 

0 = Cursor pixel data bypasses gamma correction or palette (default). 

1 = Cursor pixel data is gamma to be corrected in the pipe.

25:16

0b

RW

Write as zero

15

0b

RW

This mode causes the cursor to be rotated 180 . In addition to setting 

this bit, software must also set the base address to the lower right corner of the 

unrotated image. Only 32 bits per pixel cursors can be rotated. This field must be zero 

when the cursor format is 2 bits per pixel. 

0 = No rotation 

1 = 180 Rotation of 32 bit per pixel cursors

14:6

0b

RW

Reserved.

5

0b

RW

See following table.

4

0b

RW

Reserved.

3

0b

RW

Reserved.

2:0

0b

RW

These three bits together with bit 5 select the mode for 

cursor as shown in the following table.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h