Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

874

Datasheet

Cursor B Control Register

Default: 00000000h

4

0b

RO

This bit requests decryption to be enabled for this plane. 

This request will be qualified with the separate decryption allow message in order to 

create the decryption enable. This bit is only allowed to change on a synchronous flip, 

but once set with a synchronous flip, the bit can remain set while using asynchronous 

flips. This value is loaded into the surface base address register of the associated plane. 

Usage must conform to the rules outlined in the plane surface base address register. 

0 = Decryption request disabled (default) 

1 = Decryption request enabled

3:0

0b

RO

([DevBW] and [DevCL] Only). This field 

specifies bits 35:32 of the popup cursor physical address. If popup mode is not selected, 

this field is ignored.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESE

RVED

PI

PE

_

S

EL

E

C

T

RESE

RVE

D

_1

CUR

S

OR

_G

AM

MA_

E

NA

B

LE

RESE

RVE

D

_2

_180RO

TA

T

ION

RESE

RVE

D

_3

C

U

R

S

OR

_M

OD

E

_

SE

LE

CT

_B

IT

RESE

RVE

D

_4

CU

RS

OR_MODE

_

SELE

CT

31:30

0b

RW

Write as zero.

29:28

0b

RW

[DevBW, DevCL, DevCDV]: A state machine handles the 

synchronization of the switch to both vertical blank signals. So as far as the software is 

concerned, when both display pipes are being used, it can be switched at any time; the 

hardware will synchronize the switch. 

00 = HW cursor is attached to Display Pipe A. This is the default after reset. 

01 = HW cursor is attached to Display Pipe B. 

10 = Reserved for to Display Pipe C.  

11 = Reserved for to Display Pipe D. 

Reserved [DevBLC] and [DevCTG]: Write as zero.

27

0b

RW

Write as zero.