Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

877

Cursor B Position Register

Default: 00000000h

31:6

0b

RW

This register specifies the graphics address of the entire 

cursor. It also acts as a trigger event to force the update of active registers on the next 

display event.  

The cursor surface address must be 4K byte aligned. The cursor must be in linear 

memory, it cannot be tiled. When performing 180 rotation, this offset must be the 

difference between the last pixel of the last line of the cursor data in its unrotated 

orientation and the cursor surface address. 

A write to this register also acts as a trigger event to force the update of active registers 

from the staging registers on the next display event. Each cursor register is double-

buffered. The CPU writes to a set of holding registers. The active registers are updated 

from the holding registers following the leading edge of the vertical blank pulse. The 

update is postponed until the next vblank if a write cycle is active to any of the cursor 

registers at the time of the vblank. The update is also postponed if a write sequence is 

in progress. 

It is assumed that if the cursor mode is changed, the cursor image will also be changed. 

To prevent the cursor from appearing when it is only partially programmed, the active 

registers will not be updated until both the cursor control and base address registers 

have been programmed. If the cursor control register is written, the cursor base address 

must also be written before the change will be effective. However, the base address 

register may be changed (e.g., to change the shape of the cursor) without also writing 

to the control register. If both are to be written, the control register must be written 

first.

5

0b

RW

MBZ

4

0b

RW

This request will be qualified with the separate decryption allow 

message in order to create the decryption enable. This bit is only allowed to change on 

a synchronous flip, but once set with a synchronous flip, the bit can remain set while 

using asynchronous flips. This value is loaded into the surface base address register of 

the associated plane. Usage must conform to the rules outlined in the plane surface 

base address register. 

0 = Decryption request disabled (default) 

1 = Decryption request enabled

3:0

0b

RW

([DevBW] and [DevCL] Only). This field 

specifies bits 35:32 of the popup cursor physical address. If popup mode is not selected, 

this field is ignored.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h