Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
883
14.11.210 DSPAADDR—Offset 7017Ch
Display A Async flip Start Address Register
Access Method
Default: 00000000h
4
0b
RO
DECRYPTION_REQUEST_THIS_BIT_REQUESTS_DECRYPTION_TO_BE_ENABLE
D_FOR_THIS_PLANE: 
This request will be qualified with the separate decryption allow 
message in order to create the decryption enable. This bit is only allowed to change on 
a synchronous flip, but once set with a synchronous flip, the bit can remain set while 
using asynchronous flips. This value is loaded into the surface base address register of 
the associated plane. Usage must conform to the rules outlined in the plane surface 
base address register. 
0 = Decryption request disabled (default) 
1 = Decryption request enabled
3:0
0b
RO
POPUP_CURSOR_BASE_ADDRESS_MSBS: 
([DevBW] and [DevCL] Only). This field 
specifies bits 35:32 of the popup cursor physical address. If popup mode is not selected, 
this field is ignored.
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISP
LA
Y_A_S
TAR
T_ADDRE
S
S
_
BIT
S
RES
E
RVE
D
FLIP_
S
OURCE
D
E
CRY
PT
ION_R
E
Q
UE
ST
RE
SERV
ED_1
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:12
0b
RW
DISPLAY_A_START_ADDRESS_BITS: 
This register provides the start address of the 
display A plane or the first eye when running in stereo mode. This address must be at 
least pixel aligned. This register can be written directly through software or by 
command packets in the command stream. It represents an offset from the graphics 
memory aperture base and is mapped to physical pages through the global GTT. 
This address must be 4K aligned. When performing asynchronous flips and the display 
surface is in tiled memory, this address must be 256K aligned. This register can be 
written directly through software or by command packets in the command stream. It 
represents an offset from the graphics memory aperture base and is mapped to physical 
pages through the global GTT. 
If the device supports trusted operation and this plane is not marked trusted, the 
memory pages must not be marked NoDMA .  
Write to this register triggers async flip. The async flip address is written into the 
Display A Base Address register 0x7019C