Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

886

Datasheet

23

0b

RW

. This bit applies only to devices with a display plane C. This 

bit is set to one when the color key is used as a destination key for display C. Display 

plane C must be enabled on the same pipe and it s Z-order should be programmed to be 

behind display A for this to be set to a one.0 = Source Key applies to entire display 

plane A 

1 = Source Key applies to only pixels within the intersection between Display A and 

Display C 

[DevBLC] and [DevCTG]: Reserved

22

0b

RW

. This bit enables source keying for display A. Source keying allows a 

plane that is behind (below) this plane to show through where the display A key 

matches the display A data. This function is overloaded to provide display C destination 

keying when combined with the key window enable bit. Setting this bit is not allowed 

when the display pixel format includes an alpha channel.0 = Source key is disabled 

1 = Source key is enabled 

[DevBLC] and [DevCTG]: Reserved 

In destination keying, primary plane pixel will be made transparent when blending with 

sprite pixel as the destination if the primary src key matches with the primary pixel 

value.

21:20

0b

RW

This cause the display plane to duplicate lines and pixels sent to 

the assigned pipe. In the pixel multiply mode, the horizontal pixels are doubled and 

lines are sent twice. Asynchronous flips are not used in this mode. 

Programming Notes: 

Asynchronous flips are not permitted when pixel multiply is enabled. 

00 = No duplication 

01 = Line/pixel Doubling 

10 = Reserved 

11 = Pixel Doubling only

19

0b

RW

Software must preserve the contents of this bit.

18

0b

RW

Write as zero

17:16

0b

RW

Software must preserve the contents of this bit.

15

0b

RW

This mode causes the display plane to be rotated 180 . In 

addition to setting this bit, software must also set the base address to the lower right 

corner of the unrotated image. 

[DevCL] Do not enable 180 rotation together with Frame Buffer Compression0 = No 

rotation 

1 = 180 rotation

14

0b

RW

[DevBW, DevCL, DevCDV]:  

[DevBLC] and [DevCTG] Display A Trickle Feed Enable: 

0 = Trickle Feed Enabled - Display A data requests are sent whenever there is space in 

the Display Data Buffer.  

1 = Trickle Feed Disabled - Display A data requests are sent in bursts. 

Note: On mobile products this bit will be ignored such that Trickle Feed is always 

disabled. 

[DevELK] Must always be programmed disabled

13

0b

RW

[DevBW, DevCL, DevCDV]:  

[DevBLC] and [DevCTG] Display A Data Buffer Partitioning Control: 

0 = Display A Data Buffer will encompass Sprite A buffer space when Sprite A is 

disabled. 

1 = Display A Data Buffer will not use Sprite A buffer space when Sprite A is disabled. 

Note: When in C3xR Max FIFO mode, this bit will be ignored.

12:11

0b

RW

Reserved.