Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

887

Display A Linear Offset Register

Default: 00000000h

10

0b

RW

. This bit indicates that the display A surface data is in tiled memory. 

The tile pitch is specified in bytes in the DSPASTRIDE register. Only X tiling is supported 

for display surfaces.When this bit is set, it affects the hardware interpretation of the 

DSPATILEOFF, DSPALINOFF, and DSPASURF registers. 

0 = Display A surface uses linear memory 

1 = Display A surface uses X-tiled memory

9

0b

RW

[DevBW, DevCL, DevCDV] Write as zero  

[DevBLC, DevCTG] Asynchronous Surface Address Update Enable: This bit will enable 

asynchronous updates of the surface address when written by MMIO. The surface 

address will change with the next TLB request or when start of vertical blank is reached. 

Updates during vertical blank may not complete until after the first few active lines are 

displayed. 

Restrictions: 

No command streamer initiated surface address updates are allowed when this bit is 

enabled. 

Only one asynchronous update may be made per frame. Must wait for vertical blank 

before again writing the surface address register. 

0 = DSPASURF MMIO writes will update synchronous to start of vertical blank (default) 

1 = DSPASURF MMIO writes will update asynchronously

8:1

0b

RW

Write as zero

0

0b

RW

This bit will force the display A plane to be on 

the bottom of any sprite planes in the Z order.  

0 = Display A Z-order is determined by the other control bits in pipe A 

1 = Display A is forced to be on the bottom of any sprite planes in Z-order in pipe A

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISP

LA

Y_A_O

FFSET