Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
910
Datasheet
14.11.240 PIPEB_DSL—Offset 71000h
Display Scan Line
Access Method
Default: 00000000h
1
0b
RW
DAC_DBL_LIN_COUNTER_2_OVERRIDE_SELECT:
Project: DevIBX-B
Default Value: 0b
Value Name Description Project
0b No override No override, count value is from counter 2 All
1b Override Override mode enabled, count value is from 8-bit override value All
0
0b
RW
DAC_DBL_LIN_RGB_DAC_DFT_MODE_ENABLE:
Project: DevIBX-B
Default Value: 0b
Value Name Description Project
0b Disable Normal operation, no test mode enabled All
1b Enable RGB DAC DFT mode enabled All
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C
U
RRE
N
T
_FIELD
RE
SERV
ED
PIPE_B_DISP
LA
Y
_LINE_COUNTER
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RO
CURRENT_FIELD:
[DevBLC, DevCTG, DevCDV] Provides read back of the current field
being displayed on display pipe B.
Non-TV mode:
0 = first field (odd field)
1 = second field (even field)
TV mode:
1 = first field (odd field)
0 = second field (even field)
[DevBW and DevCL] Reserved: Read only.
30:13
0b
RO
RESERVED:
Read only.
12:0
0b
RO
PIPE_B_DISPLAY_LINE_COUNTER:
This register enables the read back of the
display vertical line counter . The display line values are from the pipe B timing
generator. They change at the leading edge of HSYNC, and can be safely read at any
time.