Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

913

28:27

0b

RW

Used to delay the frame start signal that is sent to the display 

planes. Normal operation uses the default 00 value and test modes can use the delayed 

frame start to shorten the test time. This would be set to 00 for normal operation. 

00 = Frame Start occurs on the first HBLANK after the start of VBLANK 

01 = Frame Start occurs on the second HBLANK after the start of VBLANK 

10 = Frame Start occurs on the third HBLANK after the start of VBLANK 

11 = Frame Start occurs on the forth HBLANK after the start of VBLANK

26

0b

RW

[DevVLVP] Setting this bit to 1 indicates the 

DisplayPort will output audio only. 

0 = DisplayPort will output Video or Video and Audio 

1 = DisplayPort will output Audio only

25

0b

RW

: (TEST MODE)0 = Normal Operation 

1 = Color information is ignored and border color is substituted during active region

24

0b

RW

. This bit selects which mode the pipe gamma 

correction logic works in. In the palette mode, it behaves as a 3X256x8 RAM lookup. 

VGA and indexed mode operation should use the palette in 8-bit mode. In the 10-bit 

gamma mode, it will act as a piecewise linear interpolation. Other gamma units such as 

in the overlay and sprite are unaffected by this bit.0 = 8-bit Palette Mode 

1 = 10-bit Gamma Mode

23:21

0b

RW

These bits are used for software control of interlaced behavior. 

They are updated immediately if the pipe is off, or in the vertical blank after 

programming if pipe is enabled. 

0xx = Progressive 

100 = Interlaced embedded panel using programmable vertical sync shift (2x) 

101 = Interlaced using vertical sync shift. Backup option to setting 110. (2x) 

110 = Interlaced with VSYNC/HSYNC Field Indication using legacy vertical sync shift. 

Used for SDVO. 

111 = Interlaced with Field 0 Only using legacy vertical sync shift. Not used. 

Note: VGA display modes, sDVO line stall, and Panel fitting do not work while in 

interlaced modes 

Setting the Interlaced embedded panel mode causes hardware to automatically modify 

the output to match the specifications of panels that support interlaced mode.

20

0b

RW

.0 = Normal Operation, 

display controller generate timing and refresh display panel at refresh rate  

1 = Display self-refresh mode. Display controller update frame buffer in display module 

on demand only 

19

0b

RW

. This bit when set will cause all enabled Display 

and overlay planes that are assigned to this pipe to be disabled by overriding the 

current setting of the plane enable bit, at the next VBLANK. Timing signals continue as 

they were but the screen becomes blank. Setting the bit back to a zero will then allow 

the display and overlay planes to resume on the following VBLANK.0 = Normal 

Operation 

1 = Planes assigned to this pipe are disabled.

18

0b

RW

. This bit when set will cause all enabled cursor planes that 

are assigned to this pipe to be disabled by overriding the current setting of the plane 

enable bit, at the next VBLANK. Timing signals continue as they were but the screen 

becomes blank. Setting the bit back to a zero will then allow the cursor planes to 

resume on the following VBLANK. 0 = Normal Operation 

1 = Planes assigned to this pipe are disabled.

17:16

0b

RW

These bits select how refresh rates 

are tied to CxSR on pipe B. When they are set to anything other than 00, bits 23:21 of 

this register must be programmed to 0xx. Switching between 01 and 10 settings directly 

is not allowed. Software must program this field to 00 before switching. Software is 

responsible for enabling this mode only for integrated dispay panels that support 

corresponding mode. 

00 Default no dynamic refresh rate change enabled. Software control only. 

01 Progressive-to-progressive refresh rate change enabled and tied to CxSR. Pixel clock 

values set in FPB0/FPB1 settings in the DPLLB control register and FPB0/FPB1 divider 

registers. 

10 Progressive-to-interlaced refresh rate change enabled and tied to CxSR. Pixel clock 

value does not change in this case. Scaling must be disabled in this mode. Uses 

programmable VS shift 

11 Reserved