Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
919
24
0b
RW
DISPLAY_LINE_COMPARE_ENABLE: 
0 = Pipe B Display Line Compare Status Report 
Disabled 
1 = Pipe B Display Line Compare Status report Enabled
23
0b
RW
BLM_EVENT_ENABLE: 
[DevCL, DevCTG, DevCDV]: This interrupt is generated by the 
image brightness segment comparators. Which segment cause an interrupt are 
controlled by the BLM Histogram control register. 
0 = No BLM event enabled 
1 = BLM event enabled
22
0b
RW
SPRITE_C_FLIP_DONE_INTERRUPT_ENABLE: 
This will enable the consideration of 
the Sprite C flip done interrupt status bit in the first line interrupt logic 
0 = Sprite C Flip Done Interrupt Disabled 
1 = Sprite C Flip Done Interrupt Enabled
21
0b
RW
ODD_FIELD_INTERRUPT_EVENT_ENABLE: 
. This bit should only be used when this 
pipe is in an interlaced display timing.0 = Odd Field Event disable 
1 = Odd Field Event enable
20
0b
RW
EVEN_FIELD_INTERRUPT_EVENT_ENABLE: 
. This bit should only be used when this 
pipe is in an interlaced display timing.0 = Even field Event disable 
1 = Even field Event enable
19
0b
RW
PANEL_SELF_REFRESH_PSR_INTERRUPT_ENABLE_ON_PIPE_B: 
0 = PSR 
interrupt Disabled on Pipe B 
1 = PSR Interrupt Enabled on Pipe B
18
0b
RW
START_OF_VERTICAL_BLANK_INTERRUPT_ENABLE: 
This will enable the 
consideration of the start of vertical blank interrupt status bit in the first line interrupt/
status logic. 
0 = Start of Vertical Blank Interrupt/Status Disabled 
1 = Start of Vertical Blank Interrupt/Status Enabled
17
0b
RW
PIPE_B_FRAMESTART_INTERRUPT_ENABLE: 
This will enable the consideration of 
the vertical blank interrupt status bit in the first line interrupt/status logic. 
0 = Pipe B Framestart Interrupt/Status Disabled 
1 = Pipe B Framestart Interrupt/Status Enabled
16
0b
RW
PIPE_B_HORIZONTAL_BLANK_INTERRUPT_ENABLE: 
: This will enable the 
consideration of the start of horizontal blank interrupt status bit in the first line 
interrupt/status logic0 = Start of Horizontal Blank Interrupt/Status Disabled 
1 = Start of Horizontal Blank Interrupt/Status Enabled
15
0b
RW/1C
SPRITE_D_FLIP_DONE_INTERRUPT_STATUS: 
MMIO Flip Event is completed on 
Sprite D 
0 = Sprite D Flip Not Done 
1 = Sprite D Flip Done  
AccessType: One to Clear
14
0b
RW/1C
SPRITE_C_FLIP_DONE_INTERRUPT_STATUS: 
MMIO Flip Event is completed on 
Sprite C 
0 = Sprite C Flip Not Done 
1 = Sprite C Flip Done  
AccessType: One to Clear
13
0b
RW/1C
CRC_ERROR_STATUS: 
This bit is set when a Pipe B CRC error is detected. It is cleared 
by a write of a one. 
0 = No CRC Error 
1 = CRC Error detected  
AccessType: One to Clear
12
0b
RW/1C
CRC_DONE_INTERRUPT_STATUS: 
This bit is set when Pipe B CRC calculation and 
compare are complete. It is cleared by a write of a one. 
0 = CRC Not Done 
1 = CRC Done  
AccessType: One to Clear
Bit 
Range
Default & 
Access
Field Name (ID): Description