Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

920

Datasheet

11

0b

RW/1C

This bit is set when 

the second performance counter2 generates an interrupt. It is cleared by a write of a 

one. 

0 = Second performance counter interrupt event not asserted 

1 = Second performance counter interrtup event asserted  

AccessType: One to Clear

10

0b

RW/1C

Async/Sync Flip Event is completed 

on Display Plane B 

0 = Plane B Flip Not Done 

1 = Plane B Flip Done  

AccessType: One to Clear

9

0b

RW/1C

0 = Vertical Sync not asserted 

1 = Vertical Sync asserted  

AccessType: One to Clear

8

0b

RW/1C

This bit is cleared when a write to this 

register occurs with this bit as a one. Writes with this bit as a zero has no effect on the 

value of the bit. 

0 = Display Line Compare Status not asserted 

1 = Display Line Compare Status asserted  

AccessType: One to Clear

7

0b

RW/1C

[DevCL, DevCTG, DevCDV]: This bit is cleared 

when a write to this register occurs with this bit as a one. Writes with this bit as a zero 

has no effect on the value of the bit. 

0 =DPST Interrupt has not occurred on pipe B 

1 = DPST Interrupt has occurred on pipe B  

AccessType: One to Clear

6

0b

RW

MBZ

5

0b

RW/1C

. This status bit will be set on a Odd field VBLANK 

event. This bit should only be used when this pipe is in an interlaced display timing. For 

synchronization with register updates, the actual event will occur one line after the start 

of VBLANK. To use this bit in a polling manner, clear the bit by writing a one to it 

followed by the polling loop waiting for it to become set.Note: This bit will not be set 

when pipe is in Interlaced with Field 0 Only using legacy vertical sync shift mode. 

0 = Odd Field Vertical Blank has not occurred 

1 = Odd Field Vertical Blank has occurred  

AccessType: One to Clear

4

0b

RW/1C

. This status bit will be set on a even filed 

VBLANK event. This bit should only be used when this pipe is in an interlaced display 

timing. For synchronization with register updates, the actual event will occur one line 

after the start of VBLANK. To use this bit in a polling manner, clear the bit by writing a 

one to it followed by the polling loop waiting for it to become set.Note: This bit will not 

be set when pipe is in Interlaced with Field 0 Only using legacy vertical sync shift mode. 

0 = Even Field Vertical Blank has not occurred 

1 = Even Field Vertical Blank has occurred  

AccessType: One to Clear

3

0b

RW/1C

This bit indicates interrupt is generated 

by the PSR controller and intends to send interrupt to SW driver when the PSR interrupt 

enable bit (70028h bit 22) is set. This is cleared when a write to this register occurs with 

this bit as a one. Write with this bit as a zero has no effect on the value of the bit. 

0 = PSR Interrupt has not occurred on pipe B 

1 = PSR interrupt has occurred on pipe B  

AccessType: One to Clear

2

0b

RW/1C

This status bit will be set at 

the beginning of a VBLANK event. At this point, the double buffered display registers 

flip, taking their new values. To use this bit in a polling manner, clear the bit by writing a 

one to it followed by the polling loop waiting for it to become set.  

In MIPI DSR mode, GPIO TE trigger sets the Vblank Interrupt status 

0 = Start of Vertical Blank has not occurred 

1 = Start of Vertical Blank has occurred  

AccessType: One to Clear