Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Power Management
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
93
•
The other cores are in a C1 or lower power state.
No notification to the system occurs upon entry to C1.
6.3.5.3
Package C6 State
A processor enters the package C6 low power state when:
•
At least one core is in the C6 state.
•
The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
granted permission by the platform.
•
The platform has allowed a package C6 state.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts.
core voltages reduced to zero volts.
6.3.6
Graphics Power Management
6.3.6.1
Graphics and video decoder C-State
GFX C-State (GC6) and VED C-state (VC6) are designed to optimize the average power
to the graphics and video decoder engines during times of idleness. GFX C-state is
entered when the graphics engine, has no workload being currently worked on and no
outstanding graphics memory transactions. VED S-state is entered when the video
decoder engine has no workload being currently worked on and no outstanding video
memory transactions. When the idleness condition is met, the processor will power
gate the Graphics and video decoder engines.
to the graphics and video decoder engines during times of idleness. GFX C-state is
entered when the graphics engine, has no workload being currently worked on and no
outstanding graphics memory transactions. VED S-state is entered when the video
decoder engine has no workload being currently worked on and no outstanding video
memory transactions. When the idleness condition is met, the processor will power
gate the Graphics and video decoder engines.
6.3.6.2
Intel
®
Display Power Saving Technology (Intel
®
DPST)
The Intel DPST technique achieves backlight power savings while maintaining visual
experience. This is accomplished by adaptively enhancing the displayed image while
decreasing the backlight brightness simultaneously. The goal of this technique is to
provide equivalent end-user image quality at a decreased backlight power level.
experience. This is accomplished by adaptively enhancing the displayed image while
decreasing the backlight brightness simultaneously. The goal of this technique is to
provide equivalent end-user image quality at a decreased backlight power level.
1. The original (input) image produced by the operating system or application is
analyzed by the Intel DPST subsystem. An interrupt to Intel
®
DPST software is
generated whenever a meaningful change in the image attributes is detected. (A
meaningful change is when the Intel DPST software algorithm determines that
enough brightness, contrast, or color change has occurred to the displaying images
that the image enhancement and backlight control needs to be altered.)
meaningful change is when the Intel DPST software algorithm determines that
enough brightness, contrast, or color change has occurred to the displaying images
that the image enhancement and backlight control needs to be altered.)
2. Intel DPST subsystem applies an image-specific enhancement to increase image
contrast, brightness, and other attributes.
3. A corresponding decrease to the backlight brightness is applied simultaneously to
produce an image with similar user-perceived quality (such as brightness) as the
original image. Intel DPST 5.0 has improved the software algorithms and has minor
hardware changes to better handle backlight phase-in and ensures the documented
and validated method to interrupt hardware phase-in.
original image. Intel DPST 5.0 has improved the software algorithms and has minor
hardware changes to better handle backlight phase-in and ensures the documented
and validated method to interrupt hardware phase-in.