Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

931

Display B Tiled Offset Register

Default: 00000000h

3

0b

RW

Project: 

All 

 

Default Value: 

0b 

 

 

This bit indicates if the source of the flip is CS or BCS so display can send the flip done 

response to the appropriate destination.  

 

 

ValueNameDescriptionProject 

0b 

CS 

Flip source is CS 

All 

 

1b 

BCS 

Flip source is BCS 

All 

2

0b

RW

Project: 

All 

 

Default Value: 

0b 

 

 

This bit requests decryption to be enabled for this plane. This request will be qualified 

with the separate decryption allow message in order to create the decryption enable. 

This bit is only allowed to change on a synchronous flip, but once set with a synchronous 

flip, the bit can remain set while using asynchronous flips. This value is loaded into the 

surface base address register of the associated plane. Usage must conform to the rules 

outlined in the plane surface base address register.  

1:0

0b

RW

Reserved.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h