Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
947
14.11.278 SPALINOFF—Offset 72184h
Sprite A Linear Offset Register
Access Method
Default: 00000000h
9:3
0b
RW
RESERVED_2:
Write as zero
2
0b
RW
SPRITE_A_BOTTOM:
This bit will force the Sprite A plane to be on the bottom of the Z
order. If the plane is marked as trusted, it only applies to the Z order of the trusted
planes.
0 = Sprite A Z order is determined by the other control bits
1 = Sprite A is forced to be on the bottom of the Z order.
1
0b
RW
RESERVED_3:
Reserved.
0
0b
RW
SPRITE_A_Z_ORDER:
With Sprite A and B z-order, bottom control bits, Sprite A plane
is placed in a specific z-order among other planes.
Display Pipe A Z-orders
SA
zorderSA
bottomSB
zorderSB
bottomResulting Pipe Z-order (from bottom to top)Source Keying
0000PA SA SB CAPA in Black
1000PA SB SA CAPA in Black
0001SB PA SA CAuse src keying on SB
0011SB PA SA CAuse src keying on SB
1001SB SA PA CAuse src keying on SA
1011SB SA PA CAuse src keying on SA
0100SA PA SB CAuse src keying on SA
1100SA PA SB CAuse src keying on SA
0110SA SB PA CAuse src keying on SB
1110SA SB PA CAuse src keying on SB
0: Sprite A z-order is disabled
1: Sprite A z-order is enabled
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SP
RIT
E
_A_OFFSET