Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Power Up and Reset Sequence
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
97
7
Power Up and Reset Sequence
This chapter provides information on the following topics:
7.1
SoC System States
7.1.1
System Sleeping States Control (S-states)
The SoC supports the S0, S3, S4, and S5 sleep states. S4 and S5 states are identical 
from a hardware and power perspective. The differentiation is software determined (S4 
= Suspend to Disk).
The SoC platform architecture assumes the usage of an external power management 
controller e.g., CPLD or PMIC. Some flows in this section refer to the power 
management controller for support of the S-states transitions.
The SoC sleep states are described in 
.
7.2
Power Up Sequences
7.2.1
RTC Power Well Transition (G5 to G3 States Transition)
When RTC_VCC (Real Time Clock power) is applied via RTC battery, the following 
occurs (see 
 for timing):
1. RTC_VCC ramps. ILB_RTC_TEST# should be low.
2. The system starts the real time clock oscillator.
3. A minimum of t1 units after RTC_VCC ramps, the external RTC RC circuit de-asserts 
ILB_RTC_TEST# and ILB_RTC_RTC#. The system is now in the G3 state. RTC 
oscillator is unlikely to be stable at this point.