Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
988
Datasheet
Default: 00000000h
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SP
R
IT
E
_C_SURF
A
CE_BASE
_
ADDRE
S
S
RE
SE
RVED
FLIP_SO
U
RCE
DE
CR
YPTION_RE
Q
UEST
RESE
RVE
D
_1
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:12
0b
RW
SPRITE_C_SURFACE_BASE_ADDRESS: 
This address specifies the surface base 
address. When the surface is tiled, panning is specified using (x, y) offsets in the 
DSPCTILEOFF register. When the surface is in linear memory, panning is specified using 
a linear offset in the DSPCLINOFF register. 
This address must be 4K aligned. This register can be written directly through software 
or by command packets in the command stream. It represents an offset from the 
graphics memory aperture base and is mapped to physical pages through the global 
GTT. 
If the device supports trusted operation and this plane is not marked trusted, the 
memory pages must not be marked NoDMA . 
The value in this register is updated through the command streamer during 
synchronous flips. 
[DevBW] and [DevCL]: This address must be 128K aligned for linear memory. 
11:4
0b
RW
RESERVED: 
: MBZ