Intel IQ80321 User Manual
Board Manual
57
Intel
®
IQ80321 I/O Processor Evaluation Platform
Hardware Reference Section
3.10.9
Detail Descriptions of Switches/Jumpers
3.10.9.1
Switch S7E1- 2/3
3.10.9.1.1
S7E1-2: RST_MODE
RESET MODE is latched at the de-asserting edge of P_RST# and it determines when the 80321 is held
in reset until the Intel
in reset until the Intel
®
XScale™ core Reset bit is cleared in the PCI Configuration and Status Register.
3.10.9.1.2
S7E1-3: RETRY
RETRY is latched at the de-asserting edge of P_RST# and it determines when the Primary PCI
interface disable PCI configuration cycles by signaling a Retry until the Configuration Cycle Retry bit
is cleared in the PCI Configuration and Status Register.
interface disable PCI configuration cycles by signaling a Retry until the Configuration Cycle Retry bit
is cleared in the PCI Configuration and Status Register.
3.10.9.1.3
Operation Setting Summary Descriptions
Table 36.
Switch S7E1- 2/3: General Descriptions
Switch
Association
Description
Factory Default
S7E1-2
IOP
RST_MODE: Sets IOP Reset-Mode operation.
Off
S7E1-3
IOP
RETRY: Sets IOP RETRY-Mode operation.
Off
Table 37.
Switch S7E1-2: RST_MODE: Settings and Operation Mode
S7E1-2
Operation Mode
Off
1 Pulled Up: Don't hold in reset (Default mode).
On
0 Pulled Down: Hold in reset.
Table 38.
Switch S7E1-3: RETRY: Settings and Operation Mode
S7E1-3
Operation Mode
Off
1 Pulled Up: Retry enabled (Default mode).
On
0 Pulled Down: Configuration Cycles enabled.
Table 39.
RST_MODE and RETRY Operation Setting Summary
RST_MODE
RETRY
Init Mode
Primary PCI Interface
Intel
®
80321 I/O
Processorr
0
0
Mode 0
Accepts Transactions
Held in Reset
0
1
Mode 1
Retries all Config Transactions
Held in Reset
1
0
Mode 2
Accepts Transactions
Initializes
1
1
Mode 3 (default)
Retries all Config Transactions
Initializes