SBE HighWire HW400c/2 User Manual
HighWire HW400c/2 User Reference Guide Rev 1.0
2
INTRODUCTION
The HW400c/2 is a flexible high-performance core processing platform for building
powerful processor enabled CompactPCI (CPCI) telephony and data communications
I/O solutions. Advanced features on the HW400c/2 include two PCI Telecom
Mezzanine Card (PTMC) sites for CT Bus enabled I/O interfaces that are
interconnected through a high-speed Layer 2 Gigabit Ethernet switch to the dual node
CompactPCI Packet Switched Backplane (cPSB). The HighWire core architecture
utilizes the Freescale MPC7447A PowerPC processor and Marvell Discovery™ III
system controller to provide a powerful computing environment for addressing a
wide range of communications applications.
The HW400c/2 is optimized for packet-based switch fabric system architectures and
is fully compliant with the PICMG 2.16 cPSB specification. The cPSB standard
provides a switched fabric backplane interconnection using Ethernet technology
overlaid on the standard CPCI J3 connector. Dual Gigabit Ethernet interfaces are
provided on the HW400c/2 cPSB interface to support both the high availability dual
node and reduced cost single node configurations.
Full CPCI compliance and interoperability are maintained including Hot Swap,
H.110 CT Bus and rear I/O support.
powerful processor enabled CompactPCI (CPCI) telephony and data communications
I/O solutions. Advanced features on the HW400c/2 include two PCI Telecom
Mezzanine Card (PTMC) sites for CT Bus enabled I/O interfaces that are
interconnected through a high-speed Layer 2 Gigabit Ethernet switch to the dual node
CompactPCI Packet Switched Backplane (cPSB). The HighWire core architecture
utilizes the Freescale MPC7447A PowerPC processor and Marvell Discovery™ III
system controller to provide a powerful computing environment for addressing a
wide range of communications applications.
The HW400c/2 is optimized for packet-based switch fabric system architectures and
is fully compliant with the PICMG 2.16 cPSB specification. The cPSB standard
provides a switched fabric backplane interconnection using Ethernet technology
overlaid on the standard CPCI J3 connector. Dual Gigabit Ethernet interfaces are
provided on the HW400c/2 cPSB interface to support both the high availability dual
node and reduced cost single node configurations.
Full CPCI compliance and interoperability are maintained including Hot Swap,
H.110 CT Bus and rear I/O support.
2.1 Product Description
The HW400c/2 is built on SBE’s advanced HighWire core architecture, and features
the MPC7447A PowerPC processor, Marvell Discovery III system controller, up to
1GB DDR SDRAM and Disk-on-Chip flash file system storage to meet the
demanding needs of today’s telecom and datacom applications. Additional developer
features including a serial console port and a COP emulator port help speed code
development. The HW400c/2 also fully supports the Intelligent Platform
Management Interface (IPMI) standard (PICMG 2.9) for system management.
The two expansion sites accept both CT Bus enabled PTMC modules and standard
PMC modules. PT2MC modules have access to the on-board local CT Bus and
timeslot interchange fabric allowing flexible routing of TDM timeslots both between
the PTMC sites and the H.110 backplane CT Bus. PT5MC modules also include
Gigabit Ethernet connectivity to platform resources. The HW400c/2 automatically
detects each module type to provide full mix and match support for using PT2MC,
PT5MC or PMC modules in either site.
The 32-bit 33-133 MHz PCI/PCI-X interface supports 3.3V signaling modules with
full support for both front and rear I/O access per PICMG 2.3 mapping.
In addition, a 10/100/1000 Ethernet port for system management and application
flexibility is included through a front panel RJ45 connector on the board.
Figure 1 shows the block diagram of the HW400c/2.
the MPC7447A PowerPC processor, Marvell Discovery III system controller, up to
1GB DDR SDRAM and Disk-on-Chip flash file system storage to meet the
demanding needs of today’s telecom and datacom applications. Additional developer
features including a serial console port and a COP emulator port help speed code
development. The HW400c/2 also fully supports the Intelligent Platform
Management Interface (IPMI) standard (PICMG 2.9) for system management.
The two expansion sites accept both CT Bus enabled PTMC modules and standard
PMC modules. PT2MC modules have access to the on-board local CT Bus and
timeslot interchange fabric allowing flexible routing of TDM timeslots both between
the PTMC sites and the H.110 backplane CT Bus. PT5MC modules also include
Gigabit Ethernet connectivity to platform resources. The HW400c/2 automatically
detects each module type to provide full mix and match support for using PT2MC,
PT5MC or PMC modules in either site.
The 32-bit 33-133 MHz PCI/PCI-X interface supports 3.3V signaling modules with
full support for both front and rear I/O access per PICMG 2.3 mapping.
In addition, a 10/100/1000 Ethernet port for system management and application
flexibility is included through a front panel RJ45 connector on the board.
Figure 1 shows the block diagram of the HW400c/2.
October 10, 2006
Copyright 2006, SBE, Inc.
Page
2