Renesas R61509V User Manual
R61509V
Target
Spec
Rev. 0.11 April 25, 2008, page 127 of 181
18-bit RGB Interface
The 18-bit RGB interface is selected by setting RIM = 0. The display operation is synchronized with
VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in
synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE)
allows RAM access via RGB interface.
VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in
synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE)
allows RAM access via RGB interface.
Instruction bits can be transferred only via system interface.
HOST
PROCESSOR
R61509V
18
DOTCLK
ENABLE
DB17-0
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RIM = 0
Data format for the 18-bit interface (RIM = 0)
Input
GRAM write
data
data
1 pixel
Note: Normal display in 262,144 colors
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
VSYNCX
HSYNCX
Figure 48 Example of 18-Bit RGB Interface and Data Format