Texas TMS320C67X/C67X+ DSP User Manual
Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset
LDDW
3-129
Instruction Set
SPRU733
Increments and decrements default to 1 and offsets default to 0 when no
bracketed register, bracketed constant, or constant enclosed in parentheses
is specified. Square brackets, [ ], indicate that ucst5 is left shifted by 3.
Parentheses, ( ), indicate that ucst5 is not left shifted. In other words,
parentheses indicate a byte offset rather than a doubleword offset. You must
type either brackets or parenthesis around the specified offset if you use the
optional offset parameter.
bracketed register, bracketed constant, or constant enclosed in parentheses
is specified. Square brackets, [ ], indicate that ucst5 is left shifted by 3.
Parentheses, ( ), indicate that ucst5 is not left shifted. In other words,
parentheses indicate a byte offset rather than a doubleword offset. You must
type either brackets or parenthesis around the specified offset if you use the
optional offset parameter.
The addressing arithmetic that performs the additions and subtractions
defaults to linear mode. However, for A4−A7 and for B4−B7, the mode can be
changed to circular mode by writing the appropriate value to the AMR (see
section 2.7.3, page 2-10).
defaults to linear mode. However, for A4−A7 and for B4−B7, the mode can be
changed to circular mode by writing the appropriate value to the AMR (see
section 2.7.3, page 2-10).
The destination register pair must consist of a consecutive even and odd
register pair from the same register file. The instruction can be used to load
a double-precision floating-point value (64 bits), a pair of single-precision
floating-point words (32 bits), or a pair of 32-bit integers. The least-significant
32 bits are loaded into the even-numbered register and the most-significant
32 bits (containing the sign bit and exponent) are loaded into the next register
(which is always odd-numbered register). The register pair syntax places the
odd register first, followed by a colon, then the even register (that is, A1:A0,
B1:B0, A3:A2, B3:B2, etc.).
register pair from the same register file. The instruction can be used to load
a double-precision floating-point value (64 bits), a pair of single-precision
floating-point words (32 bits), or a pair of 32-bit integers. The least-significant
32 bits are loaded into the even-numbered register and the most-significant
32 bits (containing the sign bit and exponent) are loaded into the next register
(which is always odd-numbered register). The register pair syntax places the
odd register first, followed by a colon, then the even register (that is, A1:A0,
B1:B0, A3:A2, B3:B2, etc.).
All 64 bits of the double-precision floating point value are stored in big- or little-
endian byte order, depending on the mode selected. When the LDDW instruc-
tion is used to load two 32-bit single-precision floating-point values or two
32-bit integer values, the order is dependent on the endian mode used. In little-
endian mode, the first 32-bit word in memory is loaded into the even register.
In big-endian mode, the first 32-bit word in memory is loaded into the odd regis-
ter. Regardless of the endian mode, the doubleword address must be on a
doubleword boundary (the three LSBs are zero).
endian byte order, depending on the mode selected. When the LDDW instruc-
tion is used to load two 32-bit single-precision floating-point values or two
32-bit integer values, the order is dependent on the endian mode used. In little-
endian mode, the first 32-bit word in memory is loaded into the even register.
In big-endian mode, the first 32-bit word in memory is loaded into the odd regis-
ter. Regardless of the endian mode, the doubleword address must be on a
doubleword boundary (the three LSBs are zero).
Execution
if (cond)
mem → dst
else nop
Pipeline
Stage
Stage
E1
E2
E3
E4
E5
Read
baseR,
offsetR
offsetR
Written
baseR
dst
Unit in use
.D
Instruction Type
Load
Pipeline