LSI 53C875A User Manual
PCI and External Memory Interface Timing Diagrams
6-11
Figure 6.8
Interrupt Output
6.4 PCI and External Memory Interface Timing Diagrams
through
represent signal activity when the
LSI53C875A accesses the PCI bus. This section includes timing
diagrams for access to three groups of memory configurations. The first
group applies to
diagrams for access to three groups of memory configurations. The first
group applies to
. The second group applies to
. The third group applies to
.
Note:
Multiple byte accesses to the external memory bus
increase the read or write cycle by 11 clocks for each
additional byte.
increase the read or write cycle by 11 clocks for each
additional byte.
Timing diagrams included in this section are:
•
–
–
–
–
–
–
•
–
–
–
–
CLK
IRQ/
t
3
t
1
t
2