LSI 53C875A User Manual
6-56
Electrical Specifications
Table 6.42
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes
(16-Bit Transfers) 40 MHz Clock
(16-Bit Transfers) 40 MHz Clock
Symbol
Parameter
Min
Max
Unit
t
1
Send SREQ/ or SACK/ assertion pulse width
30
–
ns
t
2
Send SREQ/ or SACK/ deassertion pulse width
30
–
ns
t
1
Receive SREQ/ or SACK/ assertion pulse width
22
–
ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width
22
–
ns
t
3
Send data setup to SREQ/ or SACK/ asserted
24
–
ns
t
4
Send data hold from SREQ/ or SACK/ asserted
34
–
ns
t
5
Receive data setup to SREQ/ or SACK/ asserted
14
–
ns
t
6
Receive data hold from SREQ/ or SACK/ asserted
24
–
ns
Table 6.43
Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock
1, 2
1. Transfer period bits (bits [6:4] in the
register) are set to zero and the Extra
Clock Cycle of Data Setup bit (bit 7 in
) is set.
2. During Ultra SCSI transfers, the value of the Extend REQ/ACK Filtering bit (
, bit 1) has no effect.
Symbol
Parameter
Min
Max
Unit
t
1
Send SREQ/ or SACK/ assertion pulse width
15
–
ns
t
2
Send SREQ/ or SACK/ deassertion pulse width
15
–
ns
t
1
Receive SREQ/ or SACK/ assertion pulse width
11
–
ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width
11
–
ns
t
3
Send data setup to SREQ/ or SACK/ asserted
12
–
ns
t
4
Send data hold from SREQ/ or SACK/ asserted
17
–
ns
t
5
Receive data setup to SREQ/ or SACK/ asserted
6
–
ns
t
6
Receive data hold from SREQ/ or SACK/ asserted
11
–
ns