LSI 53C810A User Manual

LSI

IX-2

Index

clock address incrementor bit

clock byte counter bit

clock conversion factor bits

CLSE bit

CM bit

CMP bit

,

COM bit

CON bit

,

configured as I/O bit

configured as memory bit

connected bit

,

CSF bit

CTEST0 register

CTEST1 register

CTEST2 register

CTEST4 register

CTEST5 register

CTEST6 register

cycle frame

D

DACK bit

data acknowledge status bit

data path

data request status bit

data structure address register

data transfer direction bit

dataRD bit

dataWR bit

DWR bit

DBC register

DC characteristics

DCMD register

DCNTL register

DDIR bit

destination I/O-memory enable bit

determining the data transfer rate

device select

DEVSEL/

DF[7:0] bits

DFE bit

DFIFO register

DHP bit

DIEN register

DIFFSENS SCSI signal

DIOM bit

DIP bit

disable halt on parity error or ATN bit

disable single initiator response bit

DMA byte counter register

DMA command register

DMA control register

DMA core

DMA direction bit

DMA FIFO

DMA FIFO bits

DMA FIFO empty bit

DMA FIFO register

DMA interrupt enable register

DMA interrupt pending bit

DMA mode register

DMA next address register

DMA SCRIPTS pointer register

DMA SCRIPTS pointer save register

DMA status register

DMODE register

DNAD register

DRD bit

DREQ bit

DSA register

DSI bit

DSP register

DSPS register

DSTAT register

E

ease of use

enable parity checking bit

enable read line bit

enable read multiple bit

enable response to reselection bit

enable response to selection bit

encoded destination SCSI ID bits

EPC bit

ERL bit

EXC bit

EXT bit

extend SREQ/SACK filtering bit

extra clock cycle of data setup bit

F

FBL[2:0] bits

fetch enable bit

fetch opcode bursting

FF[3:0] bits

FFL[3:0] bits

FIFO byte control bits

FIFO flags bits

FMT[3:0] bits

FRAME/

function complete bit

,

G

GEN bit

,

GEN[3:0] bits

general purpose bits

general purpose pin control register

general purpose register

general purpose timer expired bit

general purpose timer period bits

GNT/

GPCNTL register

GPIO enable bits

GPIO[1:0] bits

GPIO_EN[1:0] bits

GPREG register

grant

H

halt SCSI clock bit

HSC bit

handshake-to-handshake timer expired bit

handshake-to-handshake timer period bits

header type (HT[7:0])

high impedance mode bit

HTH bit