Intel Webcam 253668-032US User Manual
Vol. 3 8-21
MULTIPLE-PROCESSOR MANAGEMENT
Processor 1 performs two read operations, the first read is from an address outside
the 512-byte block but to be updated by processor 0, the second ready is from inside
the block of memory of string operation.
the 512-byte block but to be updated by processor 0, the second ready is from inside
the block of memory of string operation.
Processor 1 cannot perceive the later store by processor 0 until it sees all the stores
from the string operation. Example 8-13 assumes that processor 0’s store to [_z] is
not executed while the string operation has been interrupted. If the string operation
is interrupted and the store to [_z] by processor 0 is executed by the interrupt
handler, then changes to [_z] will become visible before the string operation
resumes.
Example 8-14 illustrates the visibility principle when a string operation is interrupted.
from the string operation. Example 8-13 assumes that processor 0’s store to [_z] is
not executed while the string operation has been interrupted. If the string operation
is interrupted and the store to [_z] by processor 0 is executed by the interrupt
handler, then changes to [_z] will become visible before the string operation
resumes.
Example 8-14 illustrates the visibility principle when a string operation is interrupted.
In Example 8-14, processor 0 started a string operation to write to a memory block
of 512 bytes starting at address _x. Processor 0 got interrupted after k iterations of
store operations. The address _y has not yet been updated by processor 0 when
processor 0 got interrupted. The interrupt handler that took control on processor 0
writes to the address _z. Processor 1 may see the store to _z from the interrupt
handler, before seeing the remaining stores to the 512-byte memory block that are
executed when the string operation resumes.
Example 8-15 illustrates the ordering of string operations with earlier stores. No
store from a string operation can be visible before all prior stores are visible.
of 512 bytes starting at address _x. Processor 0 got interrupted after k iterations of
store operations. The address _y has not yet been updated by processor 0 when
processor 0 got interrupted. The interrupt handler that took control on processor 0
writes to the address _z. Processor 1 may see the store to _z from the interrupt
handler, before seeing the remaining stores to the 512-byte memory block that are
executed when the string operation resumes.
Example 8-15 illustrates the ordering of string operations with earlier stores. No
store from a string operation can be visible before all prior stores are visible.
Example 8-13. String Operations Are not Reordered with later Stores
Processor 0
Processor 1
rep:stosd [ _x]
mov r1, [ _z]
mov [_z], $1
mov r2, [ _y]
Initially on processor 0: EAX == 1, ECX==128, ES:EDI ==_x
Initially [_y] == [_z] == 0, [_x] to 511[_x]== 0, _x <= _y < _x+512, _z is a separate memory
Initially [_y] == [_z] == 0, [_x] to 511[_x]== 0, _x <= _y < _x+512, _z is a separate memory
location
r1 == 1 and r2 == 0 is not allowed
r1 == 1 and r2 == 0 is not allowed
Example 8-14. Interrupted String Operation
Processor 0
Processor 1
rep:stosd [ _x] // interrupted before es:edi reach
_y
mov r1, [ _z]
mov [_z], $1 // interrupt handler
mov r2, [ _y]
Initially on processor 0: EAX == 1, ECX==128, ES:EDI ==_x
Initially [_y] == [_z] == 0, [_x] to 511[_x]== 0, _x <= _y < _x+512, _z is a separate memory
Initially [_y] == [_z] == 0, [_x] to 511[_x]== 0, _x <= _y < _x+512, _z is a separate memory
location
r1 == 1 and r2 == 0 is allowed
r1 == 1 and r2 == 0 is allowed