Intel Webcam 253668-032US User Manual

Vol. 3   11-45

MEMORY CACHE CONTROL

THEN

pre_mtrr_change();

update affected MTRR;

post_mtrr_change();

FI;

ELSE (* try to map using a variable MTRR pair *)

IF IA32_MTRRCAP.VCNT = 0

THEN return UNSUPPORTED; 

FI;

IF conflicts with current variable ranges 

THEN return RANGE_OVERLAP;

FI;

IF no MTRRs available

THEN return VAR_NOT_AVAILABLE; 

FI;

IF BASE and SIZE do not meet the power of 2 requirements for

variable MTRRs

THEN return INVALID_VAR_REQUEST; 

FI;

pre_mtrr_change();

Update affected MTRRs;

post_mtrr_change();

FI;

pre_mtrr_change()

BEGIN

disable interrupts;

Save current value of CR4;

disable and flush caches;

flush TLBs;

disable MTRRs;

IF multiprocessing

THEN maintain consistency through IPIs;

FI;

END

post_mtrr_change()

BEGIN

flush caches and TLBs;

enable MTRRs;

enable caches;

restore value of CR4;

enable interrupts;