Intel Webcam 253668-032US User Manual
19-42 Vol. 3
ARCHITECTURE COMPATIBILITY
memory. If the access does split across a cache line, it locks the bus and accesses
system memory.
I/O reads are never reordered in front of buffered memory writes on an IA-32
processor. This ensures an update of all memory locations before reading the status
from an I/O device.
system memory.
I/O reads are never reordered in front of buffered memory writes on an IA-32
processor. This ensures an update of all memory locations before reading the status
from an I/O device.
19.35 BUS LOCKING
The Intel 286 processor performs the bus locking differently than the Intel P6 family,
Pentium, Intel486, and Intel386 processors. Programs that use forms of memory
locking specific to the Intel 286 processor may not run properly when run on later
processors.
A locked instruction is guaranteed to lock only the area of memory defined by the
destination operand, but may lock a larger memory area. For example, typical 8086
and Intel 286 configurations lock the entire physical memory space. Programmers
should not depend on this.
On the Intel 286 processor, the LOCK prefix is sensitive to IOPL. If the CPL is greater
than the IOPL, a general-protection exception (#GP) is generated. On the Intel386
DX, Intel486, and Pentium, and P6 family processors, no check against IOPL is
performed.
The Pentium processor automatically asserts the LOCK# signal when acknowledging
external interrupts. After signaling an interrupt request, an external interrupt
controller may use the data bus to send the interrupt vector to the processor. After
receiving the interrupt request signal, the processor asserts LOCK# to insure that no
other data appears on the data bus until the interrupt vector is received. This bus
locking does not occur on the P6 family processors.
Pentium, Intel486, and Intel386 processors. Programs that use forms of memory
locking specific to the Intel 286 processor may not run properly when run on later
processors.
A locked instruction is guaranteed to lock only the area of memory defined by the
destination operand, but may lock a larger memory area. For example, typical 8086
and Intel 286 configurations lock the entire physical memory space. Programmers
should not depend on this.
On the Intel 286 processor, the LOCK prefix is sensitive to IOPL. If the CPL is greater
than the IOPL, a general-protection exception (#GP) is generated. On the Intel386
DX, Intel486, and Pentium, and P6 family processors, no check against IOPL is
performed.
The Pentium processor automatically asserts the LOCK# signal when acknowledging
external interrupts. After signaling an interrupt request, an external interrupt
controller may use the data bus to send the interrupt vector to the processor. After
receiving the interrupt request signal, the processor asserts LOCK# to insure that no
other data appears on the data bus until the interrupt vector is received. This bus
locking does not occur on the P6 family processors.
19.36 BUS HOLD
Unlike the 8086 and Intel 286 processors, but like the Intel386 and Intel486 proces-
sors, the P6 family and Pentium processors respond to requests for control of the bus
from other potential bus masters, such as DMA controllers, between transfers of
parts of an unaligned operand, such as two words which form a doubleword. Unlike
the Intel386 processor, the P6 family, Pentium and Intel486 processors respond to
bus hold during reset initialization.
sors, the P6 family and Pentium processors respond to requests for control of the bus
from other potential bus masters, such as DMA controllers, between transfers of
parts of an unaligned operand, such as two words which form a doubleword. Unlike
the Intel386 processor, the P6 family, Pentium and Intel486 processors respond to
bus hold during reset initialization.
19.37 MODEL-SPECIFIC EXTENSIONS TO THE IA-32
Certain extensions to the IA-32 are specific to a processor or family of IA-32 proces-
sors and may not be implemented or implemented in the same way in future proces-
sors and may not be implemented or implemented in the same way in future proces-