Intel 440GX User Manual
Intel
®
440GX AGPset Design Guide
1-6
Introduction
1.3.2.4
PCI Interface
The 82443GX PCI interface is 33 MHz Revision 2.1 compliant and supports up to five external
PCI bus masters in addition to the I/O bridge (PIIX4E).
PCI bus masters in addition to the I/O bridge (PIIX4E).
1.3.2.5
System Clocking
The 82443GX operates the system bus interface at 100 MHz, PCI at 33 MHz and AGP at
66/133 MHz. The 443GX clocking scheme uses an external clock synthesizer which produces
reference clocks for the system bus and PCI interfaces. The 82443GX produces a single 100 MHz
SDRAM clock output which is fed to a 1 to 18 clock buffer to support 1 to 4 DIMMs.
66/133 MHz. The 443GX clocking scheme uses an external clock synthesizer which produces
reference clocks for the system bus and PCI interfaces. The 82443GX produces a single 100 MHz
SDRAM clock output which is fed to a 1 to 18 clock buffer to support 1 to 4 DIMMs.
1.3.3
PCI-to-ISA/IDE Xcelerator (PIIX4E)
The PCI-to-ISA/IDE Xcelerator (PIIX4E) is a multi-function PCI device implementing a PCI-to-
ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an
Enhanced Power Management function. As a PCI-to-ISA bridge, the PIIX4E integrates many
common I/O functions found in ISA-based PC systems; a seven channel DMA Controller, two
82C59 Interrupt Controllers, an 8254 Timer/Counter, and a Real Time Clock. In addition to
Compatible transfers, each DMA channel also supports Type F transfers.
ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an
Enhanced Power Management function. As a PCI-to-ISA bridge, the PIIX4E integrates many
common I/O functions found in ISA-based PC systems; a seven channel DMA Controller, two
82C59 Interrupt Controllers, an 8254 Timer/Counter, and a Real Time Clock. In addition to
Compatible transfers, each DMA channel also supports Type F transfers.
The PIIX4E contains full support for both PC/PCI and Distributed DMA protocols implementing
PCI based DMA. The Interrupt Controller has Edge or Level sensitive programmable inputs and
fully supports the use of an external I/O Advanced Programmable Interrupt Controller (APIC) and
Serial Interrupts. Chip select decoding is provided for BIOS, Real Time Clock, Keyboard
Controller, second external Microcontroller, as well as 2 Programmable Chip Selects. The PIIX4E
provides full Plug and Play compatibility. The PIIX4E can be configured as a Subtractive Decode
bridge or as a Positive Decode bridge.
PCI based DMA. The Interrupt Controller has Edge or Level sensitive programmable inputs and
fully supports the use of an external I/O Advanced Programmable Interrupt Controller (APIC) and
Serial Interrupts. Chip select decoding is provided for BIOS, Real Time Clock, Keyboard
Controller, second external Microcontroller, as well as 2 Programmable Chip Selects. The PIIX4E
provides full Plug and Play compatibility. The PIIX4E can be configured as a Subtractive Decode
bridge or as a Positive Decode bridge.
The PIIX4E supports two IDE connectors for up to four IDE devices providing an interface for
IDE/EIDE hard disks and CD ROMs. Up to four IDE devices can be supported in Bus Master
mode. The PIIX4E contains support for “Ultra DMA/33” synchronous DMA compatible devices.
IDE/EIDE hard disks and CD ROMs. Up to four IDE devices can be supported in Bus Master
mode. The PIIX4E contains support for “Ultra DMA/33” synchronous DMA compatible devices.
The PIIX4E contains a Universal Serial Bus (USB) Host Controller that is Universal Host
Controller Interface (UHCI) compatible. The Host Controller’s root hub has two programmable
USB ports.
Controller Interface (UHCI) compatible. The Host Controller’s root hub has two programmable
USB ports.
The PIIX4E supports Enhanced Power Management, including full Clock Control, Device
Management for up to 14 devices, and Suspend and Resume logic with Power On Suspend,
Suspend to RAM or Suspend to Disk. It fully supports Operating System Directed Power
Management via the Advanced Configuration and Power Interface (ACPI) specification. The
PIIX4E integrates both a System Management Bus (SMBus) Host and Slave interface for serial
communication with other devices.
Management for up to 14 devices, and Suspend and Resume logic with Power On Suspend,
Suspend to RAM or Suspend to Disk. It fully supports Operating System Directed Power
Management via the Advanced Configuration and Power Interface (ACPI) specification. The
PIIX4E integrates both a System Management Bus (SMBus) Host and Slave interface for serial
communication with other devices.
For more information on the PIIX4E, please refer to thePIIX4 datasheet.
1.3.4 Wired for Management Initiative
Wired for Management (WfM) is an Intel initiative to improve the manageability of desktop, and
server systems. The goal of WfM is to reduce the Total Cost of Ownership (TCO) through
improved manageability in the following four technology areas:
server systems. The goal of WfM is to reduce the Total Cost of Ownership (TCO) through
improved manageability in the following four technology areas:
•
Instrumentation
•
Remote Service Boot
•
Remote Wake-Up
•
Power Management