Intel 440GX User Manual

Intel

®

 440GX AGPset Design Guide

iii

1

Introduction ................................................................................................................1-1

1.1

About This Design Guide ..............................................................................1-1

1.2

References....................................................................................................1-2

1.3

Intel

®

 Pentium

®

 II Processor / Intel

®

 440GX AGPset Overview ...................1-3

1.3.1

Intel

®

 Pentium

®

 II Processor............................................................1-3

1.3.2

Intel

®

 440GX AGPset ......................................................................1-4

1.3.2.1

System Bus Interface......................................................1-5

1.3.2.2

DRAM Interface ..............................................................1-5

1.3.2.3

Accelerated Graphics Port Interface...............................1-5

1.3.2.4

PCI Interface...................................................................1-6

1.3.2.5

System Clocking .............................................................1-6

1.3.3

PCI-to-ISA/IDE Xcelerator (PIIX4E).................................................1-6
1.3.3.1

Instrumentation ...............................................................1-7

1.3.3.2

Remote Service Boot......................................................1-7

1.3.3.3

Remote Wake-Up ...........................................................1-8

1.3.3.4

Power Management........................................................1-8

1.4

Design Recommendations............................................................................1-8
1.4.1

Voltage Definitions ...........................................................................1-8

1.4.2

General Design Recommendations .................................................1-9

1.4.3

Transitioning from Intel

“

 440BX AGPset to Intel

“

 440GX 

AGPset Design ................................................................................1-9

2

Motherboard Layout and Routing Guidelines ............................................................2-1

2.1

BGA Quadrant Assignment...........................................................................2-1

2.2

Board Description .........................................................................................2-3

2.3

Routing Guidelines........................................................................................2-5
2.3.1

GTL+ Description .............................................................................2-6

2.3.2

GTL+ Layout Recommendations .....................................................2-6

2.3.3

Single Processor Design..................................................................2-6
2.3.3.1

Single Processor Network Topology and Conditions......2-6

2.3.3.2

Single Processor Recommended Trace Lengths ...........2-7

2.3.4

Dual Processor Systems..................................................................2-8
2.3.4.1

Dual Processor Network Topology and Conditions ........2-8

2.3.4.2

Dual Processor Recommended Trace Lengths..............2-8

2.3.5

Single Processor Systems—Single-End Termination (SET) ...........2-8
2.3.5.1

Set Network Topology and Conditions ...........................2-8

2.3.5.2

SET Trace Length Requirements ...................................2-9

2.3.6

Additional Guidelines .....................................................................2-10
2.3.6.1

Minimizing Crosstalk.....................................................2-10

2.3.6.2

Practical Considerations ...............................................2-10

2.3.7

Design Methodology ......................................................................2-11

2.3.8

Performance Requirements ...........................................................2-12

2.3.9

Topology Definition ........................................................................2-13

2.3.10 Pre-Layout Simulation (Sensitivity Analysis)..................................2-13

2.4

Placement & Layout....................................................................................2-14

2.5

Post-Layout Simulation ...............................................................................2-14
2.5.1

Crosstalk and the Multi-Bit Adjustment Factor ...............................2-15