Intel 440GX User Manual
Intel
®
440GX AGPset Design Guide
3-38
Design Checklist
3.23
Layout Checklist
3.23.1
Routing and Board Fabrication
•
VRM 8.2 Support: Is the Vcc
CORE
trace/power plane sufficient to ensure Vcc
CORE
meets
specification. See the Intel
®
Pentium
®
II Datasheet for trace/power plane resistance and length
requirements.
•
V
TT
should be routed with at least a 50 mil (1.25mm) wide trace.
•
V
REF
traces should be isolated to minimize the chance of cross-talk.
•
Vcc
CORE
from the voltage regulator to Slot 1 should be an “island” as opposed to a trace.
•
Decoupling capacitor traces should be as short and wide as possible.
•
GTL+ signals should follow the layout guidelines, see AP-524 Intel
®
Pentium
®
Pro Processor
GTL+ Layout Guidelines for further information. If the recommendations are not followed,
simulations should be been run using the actual layout.
simulations should be been run using the actual layout.
•
GTL+ lines should be spaced as far apart as possible (at least 10 mils). Running GTL+ signals
closer together (5 mils) for less than 1” (2.5cm) is acceptable.
closer together (5 mils) for less than 1” (2.5cm) is acceptable.
•
There should be no CMOS/TTL signals running parallel to GTL+ signals. If they must run in
parallel, separate them on different layers with a well decoupled power or ground plane.
parallel, separate them on different layers with a well decoupled power or ground plane.
If they
must run parallel on the same layer, then separate the traces by a minimum of 25 mils.
•
Proper operation of the IDE circuit depends on the total length of the IDE bus. The total signal
length from the IDE drivers (PIIX4E pins) to the end of the IDE cables should not exceed 18”.
Therefore, the PIIX4E should be located at close as possible to the IDE headers to allow the
IDE cable to be as long as possible.
length from the IDE drivers (PIIX4E pins) to the end of the IDE cables should not exceed 18”.
Therefore, the PIIX4E should be located at close as possible to the IDE headers to allow the
IDE cable to be as long as possible.
3.23.2
Design Consideration
•
The BCLK trace to the ITP562 connector is not required to have a matched trace length to the
other BCLK signals to the Slot 1 connector or AGPset.
3.24
Applications and Add-in Hardware
3.24.1
Design Consideration
•
See the MMX™ Technology Developer’s Guide for information on the definition and use of
Intel’s MMX™ technology instruction set extension. This guide provides optimization
guidelines for developers of software utilizing the performance enhancement the instruction
set offers.
Intel’s MMX™ technology instruction set extension. This guide provides optimization
guidelines for developers of software utilizing the performance enhancement the instruction
set offers.
•
Contact your local Intel field sales representative for information on IHVs and ISVs utilizing
Intel’s MMX™ technology.
Intel’s MMX™ technology.
•
Contact your local Intel Field Sales representative for information on utilizing Intel’s latest
AGP technology.
AGP technology.