Atmel SpaceWire Router SpW-10X User Manual

Page of 155
Ref.:   UoD_SpW-10X_ 
UserManual
 
Issue:  3.4 
  
 
 
SpW-10X 
SpaceWire Router 
User Manual 
Date:  11
th
 July 2008 
 
 
Preliminary 
22
 
E xt ernal   Po rt
O utput FI FO
Input F IFO
Cros sb ar
Sw it ch
Co nt rol
L og ic
Rou ti n g
Tab le
Ti m e-Cod e
In t erface
Co nfi gu rati on
Po rt
Stat us /E rror
Regi st ers
SpaceWi re
Po rt 1
SpaceWi re
Po rt 2
SpaceWi re
Po rt 3
SpaceWi re
Po rt 4
SpaceWi re
Po rt 5
SpaceWi re
Po rt 6
SpaceWi re
Po rt 7
Con tro l
Regi st ers
SpaceWi re
Po rt 8
Spa ce Wire
Inter fac es 
Exte rna l
Input/Outp ut
S tatus
Outputs
Time -C ode
Inputs /
Outputs
E xt ernal   Po rt
O utput FI FO
Input F IFO
Exte rna l
Input/Outp ut
 
Figure 3-1 SpaceWire router block diagram 
The following paragraphs define the SpaceWire router functional logic blocks in more detail. 
3.1 SPACEWIRE PORTS 
The SpaceWire router has eight bi-directional SpaceWire links each conformant with the SpaceWire 
standard.  Each SpaceWire link is controlled by an associated link register and routing control logic.  
Network level error recovery is performed when an error is detected on the SpaceWire link as defined 
in the SpaceWire standard.  Packets received on SpaceWire links are routed by the routing control 
logic to the configuration port, other SpaceWire link ports or the external FIFO ports.  Packets with 
invalid addresses are discarded by the SpaceWire router dependent on the packet address.  The 
SpaceWire link status is recorded in the associated link register and error status is held by the router 
until cleared by a configuration command. 
3.2 EXTERNAL PORTS 
The SpaceWire router has two bi-directional parallel FIFO interfaces that can be used to connect the 
router to an external host system.  The external port FIFO is two data characters deep.  Each FIFO is