ARM AMBA NIC-301 User Manual

ARM DDI 0397G

2-16

ID031010

You can instantiate a FIFO on any channel. You can configure the FIFO to implement both 
buffering and clock domain crossing functionality. You can define the FIFO to be:
•

SYNC  1:1

•

1:n

•

n:1

•

ASYNC  m:n

•

SYNC  m:n

 

You can dynamically select this from the ASYNC m:n option if you configure a GPV.

•

programmable.

The network automatically determines that the width of the FIFO is the width of the payload. 
You can configure the depth of the FIFO to be 2-32.

All clock boundary crossings are implemented using a FIFO structure with circular read and 
write pointers, to give one cycle of latency. Data is clocked out when the pointers do not match 
on the read side.

For ASYNC, use a full synchronizer, that is, two or more cycles depending on metastability 
resolution, and the depth of the synchronizer, if it has changed.

For synchronous modes, use a single flop to synchronize each pointer, when the ratio is not 1, 
that is, both sides of m:n, and the slower side of m:1 and n:1.

For a 1:1 ratio, no extra synchronization is performed on either side.

You can change the boundary type by modifying the synchronization that is applied to the two 
pointers as they pass between domains. This ensures that the data in the FIFO is stable and safe 
to use.

To change the clocks, the synchronization must remain correct at all times. Table 2-7 shows the 
actions you must take to convert from one mode to another.

 For some changes, it is necessary to use a different setting, that is, you can only change safely 
from 1:n to 1:m by first programming the register to m:n, before the clock update.

ASYNC

Any other mode

Change the clocks then change the register.

Any mode

ASYNC

Change the register then change ASYNC. BRESP 
from the GPV implies that the update is complete.

m:n

1:1

Change the clocks, then change the register.

1:1

m:n

Change the register, then change the clocks.