ARM AMBA NIC-301 User Manual

ARM DDI 0397G

Glossary-3

ID031010

A transaction for which the write address or leading write data has transferred, but 
the write response has not yet transferred.

A transfer for which the xVALID/xREADY handshake is complete.

The non-handshake signals in a transfer.

Transaction  An entire burst of transfers, comprising an address, one or more data transfers and 

a response transfer (writes only).

An initiator driving the payload and asserting the relevant xVALID signal.

A single exchange of information. That is, with one xVALID/xREADY 
handshake.

The following AXI terms are MI attributes. To obtain optimum performance, they must be 
specified for all components with an AXI MI:

The maximum number of active transactions that a master interface can generate. 
It is specified for master interfaces that use combined storage for active write and 
read transactions. If not specified then it is assumed to be equal to the sum of the 
write and read issuing capabilities.

The maximum number of different ARID values that an MI can generate for all 
active read transactions at any one time.

The number of bits in the ARID bus.

The maximum number of active read transactions that an MI can generate.

The maximum number of different AWID values that an MI can generate for all 
active write transactions at any one time.

The number of bits in the AWID and WID buses.

The number of active write transactions for which the MI is capable of 
transmitting data. This is counted from the earliest transaction.

The maximum number of active write transactions that an MI can generate.