Access PCI-IDI-XX User Manual

Chapter 5: Programming

The base address is assigned by the computer system during installation and will fall on an eight byte
boundary. The card’s read and write functions are as follows:

Address

Read

Write

Base Address + 0

Port 0 Low Byte

N/A

Base Address + 1

Port 0 High Byte

N/A

Base Address + 2

Port 1 Low Byte

N/A

Base Address + 3

N/A

Base Address + 4

Port 1 High Byte

N/A

Base Address + 5

Port 2 Low Byte

N/A

Base Address + 6

Port 2 High Byte

N/A

Base Address + 7

IRQ Status Register/IRQ Clear

IRQ Enable/Disable

Note: Base + 7 bit 7 only applies to COS (“C”) boards

Read Base + 0 (+1, +2, +4, +5, +6)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

D7 of input
data

D6 of input
data

D5 of input
data

D4 of input
data

D3 of input
data

D2 of input
data

D1 of input
data

D0 of input
data

Reading a byte from the Port Data Base Address reads the 8 bits associated with that half of a port. The
Addresses labeled “Low Byte” are associated with pins 1 through 25, and the Addresses labeled “High
Byte” are associated with pin 26 through 50, as shown in Chapter 6, connector pin assignments.

Writing to these addresses has no effect.

Address Base +7 is used to control and monitor Change-of-State IRQs. To enable COS IRQs, write a “1"
to bit 7; disable by writing “0" to bit 7. This enable status can be read back; that is, a read from Base +7
will show bit 7 High (“1") while COS IRQs are enabled. While COS IRQs are enabled, any change of input
level (low-to-high or high-to-low) on any of the 48 bits will cause an IRQ to be generated. After an IRQ is
generated, bit 6 of Base +7 will be set Low (“0"), which can be used to confirm that a shared interrupt was
generated by this card. Any read of Base +7 will clear the IRQ latch and return bit 6 to its High (“1") state.

Please note: Enabling or Disabling IRQs does not clear the IRQ latch. If you disable IRQs while one is
pending, it is still required to read from Base +7 to clear the pending IRQ.

Read Base + 7: COS Status Register