Delta Tau GEO BRICK LV User Manual
Turbo PMAC User Manual
52
Setting Up Feedback and Master Position Sensors
Encoder Sampling Clock Frequency: E34 – E38, I7m03, I6803, MI903, MI907
After the front-end processing through the differential line receivers, the quadrature encoder inputs are
sampled by digital logic in the Turbo PMAC Servo IC or MACRO IC at a rate determined by the
frequency of the SCLK encoder sample clock” which is user settable. The higher the SCLK frequency,
the higher the maximum permissible count rate; the lower the SCLK frequency, the more effective the
digital delay noise filter is.
sampled by digital logic in the Turbo PMAC Servo IC or MACRO IC at a rate determined by the
frequency of the SCLK encoder sample clock” which is user settable. The higher the SCLK frequency,
the higher the maximum permissible count rate; the lower the SCLK frequency, the more effective the
digital delay noise filter is.
Each encoder input channel has a digital delay filter consisting of three cascaded D-flip-flops on each
line, with a best two-of-three voting scheme on the outputs of the flip-flops. The flip-flops are clocked by
the SCLK signal. This filter does not pass through a state change that only lasts for one SCLK cycle; any
change this narrow should be a noise spike. In doing this, the filter delays actual transitions by two SCLK
cycles – a trivial delay in virtually all systems.
line, with a best two-of-three voting scheme on the outputs of the flip-flops. The flip-flops are clocked by
the SCLK signal. This filter does not pass through a state change that only lasts for one SCLK cycle; any
change this narrow should be a noise spike. In doing this, the filter delays actual transitions by two SCLK
cycles – a trivial delay in virtually all systems.
If both the A and B channels change state at the decode circuitry (post-filter) in the same SCLK cycle, an
unrecoverable error to the counter value will result. The ASIC hardware notes this problem by setting
and latching the “encoder count error” bit in the channel’s status word. The problem can also be detected
by capturing the count value each revolution on the index pulse and seeing whether the correct number of
counts have elapsed.
unrecoverable error to the counter value will result. The ASIC hardware notes this problem by setting
and latching the “encoder count error” bit in the channel’s status word. The problem can also be detected
by capturing the count value each revolution on the index pulse and seeing whether the correct number of
counts have elapsed.
Encoder Digital Delay Filter
The SLCK frequency must be at least four times higher than the maximum encoder cycle (line) frequency
input, regardless of the quadrature decoding method used (with the most common times-4 decode, the
SCLK frequency must be at least as high as the count rate). In actual use, due to imperfections in the
input signals, a 20 – 25% safety margin should be used.
input, regardless of the quadrature decoding method used (with the most common times-4 decode, the
SCLK frequency must be at least as high as the count rate). In actual use, due to imperfections in the
input signals, a 20 – 25% safety margin should be used.
The default SCLK frequency of 9.83 MHz is acceptable for virtually all applications. It can accept
encoder signal cycle frequencies of up to about 2 MHz (8 MHz count rates) – with safety margin – and
still provide decent digital filtering. This frequency may be changed by factors of two, up to 19.66 or
39.32 MHz on most designs, or down to as low as 1.25 MHz or 306 kHz on most designs. On some
designs, an external SCLK signal can be provided. If very high encoder count rates are required, the
SCLK frequency may have to be raised; if better filtering is required to prevent count errors, the SCLK
frequency may have to be lowered.
encoder signal cycle frequencies of up to about 2 MHz (8 MHz count rates) – with safety margin – and
still provide decent digital filtering. This frequency may be changed by factors of two, up to 19.66 or
39.32 MHz on most designs, or down to as low as 1.25 MHz or 306 kHz on most designs. On some
designs, an external SCLK signal can be provided. If very high encoder count rates are required, the
SCLK frequency may have to be raised; if better filtering is required to prevent count errors, the SCLK
frequency may have to be lowered.