Sundance Spas ST201 User Manual
ST201
Fast Ethernet MAC
See Sundance Technology’s website at www.sundanceti.com for the latest information.
Sundance Technology
Publication:
2
Rev: A
Date:
November 1998
PRELIMINARY draft 2
FEATURES
•
Single chip 10/100BASE, half or full duplex
Ethernet Media Access Controller
Ethernet Media Access Controller
•
IEEE 802.3u compliant MII
•
IEEE 802.3x full duplex flow control
•
PCI Bus master scatter/gather DMA on any
byte boundary
byte boundary
•
On-chip transmit and receive FIFO buffers
•
On-chip LED drivers
•
Power management capabilities for ACPI
1.0 compliant systems
1.0 compliant systems
•
WakeOnLAN support
•
Management statistics gathering
•
IP multicast receive and filter support using
64 bit hash table
64 bit hash table
•
Receive early interrupt
•
Transmit polling
•
Auto pad insertion for short packets
•
Programmable minimum Inter Packet Gap
•
Programmable transmit and receive FIFO
watermarks
watermarks
•
On-chip crystal oscillator
•
3.3V CMOS with 5V tolerant I/O
•
0.35
µ
m technology
•
128-pin PQFP
GENERAL DESCRIPTION
The ST201 is a single-chip, full duplex, 10/
100Mbps Ethernet MAC incorporating a 32-bit PCI
including bus master support. The ST201 is
designed for use in a variety of applications rang-
ing from workstation NICs, networking equipment
such as switches or routers, and other systems uti-
lizing a PCI bus which require network connectivity
to an Ethernet or Fast Ethernet LAN.
100Mbps Ethernet MAC incorporating a 32-bit PCI
including bus master support. The ST201 is
designed for use in a variety of applications rang-
ing from workstation NICs, networking equipment
such as switches or routers, and other systems uti-
lizing a PCI bus which require network connectivity
to an Ethernet or Fast Ethernet LAN.
The ST201 includes a PCI bus interface unit, IEEE
802.3 compliant MAC, transmit and receive FIFO
buffers, IEEE 802.3u compliant MII, serial Electri-
cally EEPROM interface, expansion ROM inter-
face, and LED drivers.
802.3 compliant MAC, transmit and receive FIFO
buffers, IEEE 802.3u compliant MII, serial Electri-
cally EEPROM interface, expansion ROM inter-
face, and LED drivers.
The ST201 implements a rich set of control and
status registers. Accessible via the PCI interface,
these registers provide a host system visibility into
status registers. Accessible via the PCI interface,
these registers provide a host system visibility into
the features and operating state of the ST201. Net-
work management statistics are also recorded, and
host access to registers of the PHY device are
facilitated through the ST201’s PCI interface.
work management statistics are also recorded, and
host access to registers of the PHY device are
facilitated through the ST201’s PCI interface.
The ST201 supports several features for use in
“Green PCs” or systems where control over system
power consumption is desired. The ST201 sup-
ports several power down states, and the ability to
issue a system “wake event” via reception of
unique, user defined Ethernet frames. In addition,
the ST201 can assert a wake event in response to
changes in the Ethernet link status.
“Green PCs” or systems where control over system
power consumption is desired. The ST201 sup-
ports several power down states, and the ability to
issue a system “wake event” via reception of
unique, user defined Ethernet frames. In addition,
the ST201 can assert a wake event in response to
changes in the Ethernet link status.