Intel Video Game Controller Intel Gigabit Ethernet Controllers User Manual

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This section explains the registers provided for diagnostic access.

These registers enable system level integration and debugging, including the ability to access all 
internal memories. This information is often critical in determining failure modes and in 

developing software workarounds.

At a diagnostic level, all of the major internal data structures visible to and controllable by 

software, including all of the FIFO space. However, interlocks are not provided for any operations, 
so diagnostic accesses need to be performed under very controlled circumstances.

The internal data FIFO pointers are visible through the head and tail diagnostic data FIFO registers 
(see 

). Diagnostics software uses these FIFO pointers to confirm correct operation and 

to directly write packets into, or directly read out of, the FIFO.

These registers are available for diagnostic purposes only and should not be written during normal 

operation.

All of the FIFO data is visible through the PBM register. Locations can be accessed as 32-bit or 64-

bit words. Refer to 

 for details.

One loopback mode is provided in the Ethernet controller to assist with system and device debug. 
This loopback mode is enabled via RCTL.LBM control bits. The Ethernet controller must be 

operating in full-duplex mode for loopback.