Lucent Technologies MN10285K User Manual
Closed-Caption Decoder
Closed-Caption Decoder Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
248
Panasonic
CLPCND1: Clamping Control Signal Status Register 1
x’007EDC’
(CLPCNDW
x’007EFC’)
This register is for monitoring the status of the clamping current source
switch shown in figure 9-5 on page 229. An N-channel transistor is on
when the associated bit (PEDOWN, XPEDOWN, CLPN, or SAFEN) is 1.
A P-channel transistor is on when the associated bit (PEDUP, XPEDUP,
CLPP, or SAFEP) is 0.
switch shown in figure 9-5 on page 229. An N-channel transistor is on
when the associated bit (PEDOWN, XPEDOWN, CLPN, or SAFEN) is 1.
A P-channel transistor is on when the associated bit (PEDUP, XPEDUP,
CLPP, or SAFEP) is 0.
SAFEP: Low clamping control pulse for high current source (P-channel)
SAFEN: Low clamping control pulse for high current source (N-channel)
CLPP: High clamping control pulse for high current source (P-channel)
CLPN: High clamping control pulse for high current source (N-channel)
XPEDUP: Clamping control pulse for medium current source (P-channel)
XPEDOWN: Clamping control pulse for medium current source (N-channel)
PEDUP: Clamping control pulse for low current source (P-channel)
PEDOWN: Clamping control pulse for low current source (N-channel)
SBFNUM: Sampling Start Position Register
x’007E4C’
(SBFNUMW
x’007E6C’)
SBFNUM[10:0]: Detected position of start bit flag (detected by the hardware)
TESTA: Test Register
x’007E4E’
(TESTA
x’007E6E’)
SLICE[7:0]: Slicing value (either from hardware calculation or software setting)
DATAG: Data window (for capturing the caption data)
CRI2G: CRI window 2 (for detecting the sampling cycle position)
CRI1G: CRI window 1 (for calculating the maximum and minimum values)
ACQG: ACQ window (for setting the H interval for data detection)
SLDSAMP: Caption data sampling pulse
FCPIN: Start position for start bit detection (software setting)
FCP: Start position for start bit detection (hardware calculation)
SLD: Sliced data from the CVBS input signal
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
SAFEP
SAFE
N
CLPP
CLPN
XPED
UP
XPE
DOWN
PED
UP
PE
DOWN
Reset:
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
SBF
NUM
10
SBF
NUM
9
SBF
NUM
8
SBF
NUM
7
SBF
NUM
6
SBF
NUM
5
SBF
NUM
4
SBF
NUM
3
SBF
NUM
2
SBF
NUM
1
SBF
NUM
0
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SLICE
7
SLICE
6
SLICE
5
SLICE
4
SLICE
3
SLICE
2
SLICE
1
SLICE
0
DATA
G
CRI2G CRI1G ACQG
SLD
SAMP
FCPIN
FCP
SLD
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R