Lucent Technologies MN10285K User Manual

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An interrupt controller external to the core controls all nonmaskable and 

maskable interrupts except reset. There are a maximum of sixteen interrupt 
classes (class 0 to 15). Each class can have up to four interrupt factors and any of 

seven priority levels

.

The CPU checks the processor status word to determine whether or not to accept 
an interrupt request. If it accepts the request, automatic hardware servicing 

begins and the contents of the program counter and other necessary registers are 
pushed to the stack. The program then looks up and branches to the entry address 

of the interrupt service routine for the interrupt that occurred.

Note:

Interrupt control hardware configuration varies between products.

0

1

2

3

4

5

6

Interrupt Masking

Nonmaskable Interrupt

Receive

Reset

Receive

Interrupt Enable

Maskable Interrupt

Receive

Reset

CPU Core

4

Group 4

Maskable Interrupt Controllers

Maskable Interrupt

Control Registers (xx ICR)

4

External NMI pin input
Watchdog timer
Undefined instruction
Interrupt occurred,
but no vector exists

Maskable interrupts
Max. 240 vectors

External pin interrupts
Peripheral interupts

Group 63

Maskable Interrupt Controllers

Maskable Interrupt

Control Registers (xx ICR)

Interrupt Controller

4

Groups 0-3

Nonmaskable Interrupt Controllers

  Nonmaskable Interrupt

Control Registers (NMICR)

(

Nonmaskable interrupts

)

(

)

(WDICR)

(UNICR)

(EIICR)

Hardware processing

Push PC, PSW

Interrupt

Main program

x'080008'

Interrupt service routine
Header resets interrupt vector

Interrupt preprocessing

Push registers, branch to entry address, etc.

JMP, etc.

Max. 6 machine cycles

7 machine cycles