Lucent Technologies MN10285K User Manual
I
2
C Bus Controller
I
2
C Interface Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
303
Panasonic
13.6.2.3 Setting Up the Second Interrupt
The master sends an ACK = 0 signal, so the microcontroller must send the next
data byte. Set up the transmission data as follows:
The master sends an ACK = 0 signal, so the microcontroller must send the next
data byte. Set up the transmission data as follows:
■
To set up the interrupt:
Set the I2C0ICH and I2C0ICL register pair (x’00FC9C’) to x’0100’. This
enables I
2
C interrupts and clears the previous interrupt request.
■
To set up the I
2
C registers:
1.
Read the I2CDREC register (x’007E42’) to determine the I
2
C bus controller
status. The previous read from I2CDREC cleared the AAS, so AAS should
be 0.
be 0.
2.
Set the I2CDTRM register (x’007E40’) to x’01AA0’. This sets STA to 0,
STP to 0, ACK to 1, and the transmission data to x’AA’. The microcontroller
STP to 0, ACK to 1, and the transmission data to x’AA’. The microcontroller
does not need to issue an ACK signal in this transfer, so the ACK bit should
be 1.
be 1.
3.
Begin transmitting data in sync with the clock from the master.
13.6.2.4 Setting Up the Third Interrupt
The master send an ACK = 1 signal, then issues a stop condition, ending the
communication.
The master send an ACK = 1 signal, then issues a stop condition, ending the
communication.
Note:
The circled areas are signals output from the MN102H75K/85K.
Figure 13-8 Waveform for Slave Receiver Transitioning to Slave Transmitter
S
R/W
0
P
Data
(slave address)
(slave address)
1
1
1
0
ACK
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
ACK
1
1
1
SDA
SCL
0
0
0
1
ACK