Lucent Technologies MN102H75K User Manual
Serial Interfaces
Serial Interface Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
139
Panasonic
5.6.5
Setting Up I
2
C Reception Using Serial Interface 0
This example illustrates the microcontroller as a master receiver in the I
2
C mode,
using the SBO0 and SBT0 pins.
When initiating master receiver mode, your program must always first transmit a
byte of data. The master reception occurs during the interrupt service routine that
runs after the data is transmitted. For an example setup of master transmission,
runs after the data is transmitted. For an example setup of master transmission,
■
To set up the I
2
C interface:
You do not need to enable
reception if it is already enabled
by the initial settings. You can
also omit any settings already in
also omit any settings already in
place from the transmission
sequence.
The parity bits serve as the ACK
signal. To output an ACK = 1 sig-
nal, select a fixed parity of 1. To
nal, select a fixed parity of 1. To
output an ACK = 0 signal, select
a fixed parity of 0. Select a parity
of none if there is no ACK signal
of none if there is no ACK signal
1.
During the interrupt service routine for the serial transmission end, enable
reception by setting the SC0REN bit of SC0CTR to 1.
2.
Select ACK output of 1.
To set up data reception:
1.
Write a dummy data bit, x’FF’, to the serial port 0 transmit/receive buffer.
This sets the SBO0 signal high and initiates the master receiver mode.
This sets the SBO0 signal high and initiates the master receiver mode.
2.
During the service routine for the serial reception interrupt, the CPU reads
the transmit/receive buffer to retrieve the reception data. (A transmission
the transmit/receive buffer to retrieve the reception data. (A transmission
interrupt can serve as a reception interrupt.)
■
To set up the stop sequence:
1.
Set the SC0IIC bit of SC0CTR to 0 to signal the stop sequence.
2.
When you signal the stop sequence, the data reception is still in progress.
After the stop sequence is output, you must disable reception and reinitialize
reception for succeeding bytes.
reception for succeeding bytes.
Figure 5-14 shows an example timing chart.
■
Figure 5-14 Master Receiver Timing in I
2
C Mode (with ACK)
b7 b6 b5 b4 b3 b2 b1 b0
b6 b5 b4 b3 b2 b1 b0
ACK
b7
ACK
Dummy data transmission for reception
Tx interrupt request
Stop detection bit = 1
Start detection bit = 1
I
2
C sequence
output bit
Write to
SC0TRB
SBO0 output
SBT0 output
Rx settings
Tx interrupt request
Data rx
Stop sequence