Fujitsu MPG3204AH User Manual
C141-E112-01EN
5 - 85
b) Device pausing an Ultra DMA data out burst
1)
The device shall not pause an Ultra DMA burst until at least one data word of an Ultra
DMA burst has been transferred.
DMA burst has been transferred.
2)
The device shall pause an Ultra DMA burst by negating DDMARDY-.
3)
The host shall stop generating HSTROBE edges within t
RFS
of the device negating
DDMARDY-.
4)
If the device negates DDMARDY- within t
SR
after the host has generated an HSTROBE
edge, then the device shall be prepared to receive zero or one additional data words. If
the device negates DDMARDY- greater than t
the device negates DDMARDY- greater than t
SR
after the host has generated an
HSTROBE edge, then the device shall be prepared to receive zero, one or two additional
data words. The additional data words are a result of cable round trip delay and t
data words. The additional data words are a result of cable round trip delay and t
RFS
timing for the host.
5)
The device shall resume an Ultra DMA burst by asserting DDMARDY-.
5.5.4.4 Terminating an Ultra DMA data out burst
a) Host terminating an Ultra DMA data out burst
The following stops shall occur in the order they are listed unless otherwise specifically
allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements):
allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements):
1)
The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE
edges.
edges.
2)
The host shall assert STOP no sooner than t
SS
after it last generated an HSTROBE edge.
The host shall not negate STOP again until after the Ultra DMA burst is terminated.
3)
The device shall negate DMARQ within t
LI
after the host asserts STOP. The device shall
not assert DMARQ again until after the Ultra DMA burst is terminated.
4)
The device shall negate DDMARDY- with t
LI
after the host has negated STOP. The
device shall not assert DDMARDY- again until after the Ultra DMA burst termination is
complete.
complete.
5)
If HSTROBE is negated, the host shall assert HSTROBE with t
LI
after the device has
negated DMARQ. No data shall be transferred during this assertion. The device shall
ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra
DMA burst is terminated.
ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra
DMA burst is terminated.
6)
The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5)
7)
The host shall negate DMACK- no sooner than t
MLI
after the host has asserted
HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no
sooner than t
sooner than t
DVS
after placing the result of its CRC calculation on DD (15:0).
8)
The device shall latch the host's CRC data from DD (15:0) on the negating edge of
DMACK-.
DMACK-.