User ManualTable of ContentsList of Figures5List of Tables9Overview131.1 General Description131.2 Features14Architecture Overview172.1 GX1 Module172.1.1 Memory Controller172.1.2 Fast-PCI Bus222.1.3 Display222.2 Video Processor Module222.2.1 GX1 Module Interface222.2.2 Video Input Port222.2.3 Core Logic Module Interface222.2.4 CRT DAC222.3 Core Logic Module232.3.1 Other Interfaces of the Core Logic Module232.4 SuperI/O Module232.5 Clock, Timers, and Reset Logic242.5.1 Reset Logic242.5.1.1 Power-On Reset242.5.1.2 System Reset24Signal Definitions253.1 Ball Assignments273.2 Strap Options433.3 Multiplexing Configuration443.4 Signal Descriptions483.4.1 System Interface483.4.2 Memory Interface Signals503.4.3 Video Port Interface Signals513.4.4 CRT/TFT Interface Signals523.4.5 ACCESS.bus Interface Signals523.4.6 PCI Bus Interface Signals533.4.7 Sub-ISA Interface Signals573.4.8 Low Pin Count (LPC) Bus Interface Signals583.4.9 IDE Interface Signals593.4.10 Universal Serial Bus (USB) Interface Signals603.4.11 Serial Ports (UARTs) Interface Signals603.4.12 Parallel Port Interface Signals623.4.13 Fast Infrared (IR) Port Interface Signals633.4.14 AC97 Audio Interface Signals643.4.15 Power Management Interface Signals643.4.16 GPIO Interface Signals663.4.17 Debug Monitoring Interface Signals673.4.18 JTAG Interface Signals673.4.19 Test and Measurement Interface Signals683.4.20 Power, Ground and No Connections68General Configuration Block714.1 Configuration Block Addresses714.2 Multiplexing, Interrupt Selection, and Base Address Registers724.3 WATCHDOG794.3.1 Functional Description794.3.1.1 WATCHDOG Timer794.3.2 WATCHDOG Registers804.3.2.1 Usage Hints804.4 High-Resolution Timer814.4.1 Functional Description814.4.2 High-Resolution Timer Registers814.4.2.1 Usage Hints814.5 Clock Generators and PLLs834.5.1 27 MHz Crystal Oscillator844.5.2 GX1 Module Core Clock854.5.3 Internal Fast-PCI Clock854.5.4 SuperI/O Clocks864.5.5 Core Logic Module Clocks864.5.6 Video Processor Clocks864.5.7 Clock Registers87SuperI/O Module895.1 Features905.2 Module Architecture915.3 Configuration Structure/Access925.3.1 Index-Data Register Pair925.3.2 Banked Logical Device Registers925.3.3 Default Configuration Setup935.3.4 Address Decoding935.4 Standard Configuration Registers945.4.1 SIO Control and Configuration Registers975.4.2 Logical Device Control and Configuration985.4.2.1 LDN 00h - Real-Time Clock985.4.2.2 LDN 01h - System Wakeup Control1005.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 31015.4.2.4 LDN 03h and 08h - Serial Ports 1 and 21025.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 21035.4.2.6 LDN 07h - Parallel Port1045.5 Real-Time Clock (RTC)1055.5.1 Bus Interface1055.5.2 RTC Clock Generation1055.5.2.1 Internal Oscillator1055.5.2.2 External Oscillator1065.5.2.3 Timing Generation1065.5.2.4 Timekeeping1075.5.2.5 Alarms1075.5.2.6 Power Supply1085.5.2.7 System Power States1095.5.2.8 Oscillator Activity1095.5.2.9 Interrupt Handling1105.5.2.10 Battery-Backed RAMs and Registers1105.5.3 RTC Registers1115.5.3.1 Usage Hints1155.5.4 RTC General-Purpose RAM Map1155.6 System Wakeup Control (SWC)1165.6.1 Event Detection1165.6.1.1 Audio Codec Event1165.6.1.2 CEIR Address1165.6.2 SWC Registers1175.7 ACCESS.bus Interface1215.7.1 Data Transactions1215.7.2 Start and Stop Conditions1215.7.3 Acknowledge (ACK) Cycle1225.7.4 Acknowledge After Every Byte Rule1235.7.5 Addressing Transfer Formats1235.7.6 Arbitration on the Bus1235.7.7 Master Mode1235.7.7.1 Master Stop1245.7.8 Slave Mode1255.7.9 Configuration1255.7.10 ACB Registers1265.8 Legacy Functional Blocks1295.8.1 Parallel Port1295.8.1.1 Parallel Port Register and Bit Maps1295.8.2 UART Functionality (SP1 and SP2)1315.8.2.1 UART Mode Register Bank Overview1315.8.2.2 SP1 and SP2 Register and Bit Maps for UART Functionality1315.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality1355.8.3.1 IR/SP3 Mode Register Bank Overview1355.8.3.2 IRCP/SP3 Register and Bit Maps135Core Logic Module1416.1 Feature List1416.2 Module Architecture1426.2.1 Fast-PCI Interface to External PCI Bus1436.2.1.1 Processor Mastered Cycles1436.2.1.2 External PCI Mastered Cycles1436.2.1.3 Core Logic Internal or Sub-ISA Mastered Cycles1436.2.1.4 External PCI Bus1436.2.1.5 Bus Master Request Priority1436.2.2 PSERIAL Interface1436.2.2.1 Video Retrace Interrupt1446.2.3 IDE Controller1446.2.3.1 IDE Configuration Registers1446.2.3.2 PIO Mode1446.2.3.3 Bus Master Mode1456.2.3.4 UltraDMA/33 Mode1466.2.4 Universal Serial Bus1476.2.5 Sub-ISA Bus Interface1476.2.5.1 Sub-ISA Bus Cycles1486.2.5.2 Sub-ISA Support of Delayed PCI Transactions1486.2.5.3 Sub-ISA Bus Data Steering1496.2.5.4 I/O Recovery Delays1496.2.5.5 ISA DMA1506.2.5.6 ROM Interface1516.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing1516.2.6 AT Compatibility Logic1526.2.6.1 DMA Controller1526.2.6.2 Programmable Interval Timer1546.2.6.3 Programmable Interrupt Controller1556.2.7 I/O Ports 092h and 061h System Control1566.2.7.1 I/O Port 092h System Control1576.2.7.2 I/O Port 061h System Control1576.2.7.3 SMI Generation for NMI1576.2.8 Keyboard Support1576.2.8.1 Fast Keyboard Gate Address 20 and CPU Reset1576.2.9 Power Management Logic1586.2.9.1 CPU States1586.2.9.2 Sleep States1596.2.9.3 Power Planes Control1606.2.9.4 Power Management Events1606.2.9.5 Usage Hints1616.2.10 Power Management Programming1626.2.10.1 APM Support1626.2.10.2 CPU Power Management1626.2.10.3 Peripheral Power Management1646.2.10.4 Power Management Programming Summary1666.2.11 GPIO Interface1676.2.12 Integrated Audio1676.2.12.1 Data Transport Hardware1676.2.12.2 AC97 Codec Interface1706.2.12.3 VSA Technology Support Hardware1716.2.12.4 IRQ Configuration Registers1736.2.12.5 LPC Interface1736.2.12.6 LPC Interface Signal Definitions1746.2.12.7 Cycle Types1746.2.12.8 LPC Interface Support1746.3 Register Descriptions1756.3.1 PCI Configuration Space and Access Methods1756.3.2 Register Summary1766.4 Chipset Register Space1906.4.1 Bridge, GPIO, and LPC Registers - Function 01906.4.1.1 GPIO Support Registers2236.4.1.2 LPC Support Registers2276.4.2 SMI Status and ACPI Registers - Function 12356.4.2.1 SMI Status Support Registers2366.4.2.2 ACPI Support Registers2456.4.3 IDE Controller Registers - Function 22546.4.3.1 IDE Controller Support Registers2586.4.4 Audio Registers - Function 32606.4.4.1 Audio Support Registers2616.4.5 X-Bus Expansion Interface - Function 52756.4.5.1 X-Bus Expansion Support Registers2786.4.6 USB Controller Registers - PCIUSB2806.4.7 ISA Legacy Register Space293Video Processor Module3077.1 Module Architecture3087.2 Functional Description3097.2.1 Video Input Port (VIP)3117.2.1.1 Direct Video Mode3117.2.1.2 Capture Video Mode3127.2.1.3 Capture VBI Mode3147.2.2 Video Block3157.2.2.1 Video Input Formatter3157.2.2.2 Horizontal Downscaler with 4-Tap Filtering3167.2.2.3 Line Buffers3177.2.2.4 Formatter3177.2.2.5 2-Tap Vertical and Horizontal Upscalers3177.2.3 Mixer/Blender Block3187.2.3.1 YUV to RGB CSC in Video Data Path3197.2.3.2 Gamma Correction3197.2.3.3 Color/Chroma Key3197.2.3.4 Color/Chroma Key and Mixer/Blender3207.2.4 VESA DDSC2B and DPMS Support3237.2.5 Integrated DACs3237.2.6 TFT Interface3247.2.7 Integrated PLL3257.3 Register Descriptions3267.3.1 Register Summary3267.3.2 Video Processor Registers - Function 43297.3.2.1 Video Processor Support Registers - F4BAR03317.3.2.2 VIP Support Registers - F4BAR2345Debugging and Monitoring3498.1 Testability (JTAG)3498.1.1 Mandatory Instruction Support3498.1.2 Optional Instruction Support3498.1.3 JTAG Chain349Electrical Specifications3519.1 General Specifications3519.1.1 Electro Static Discharge (ESD)3519.1.2 Power/Ground Connections and Decoupling3519.1.3 Absolute Maximum Ratings3519.1.4 Operating Conditions3529.1.5 DC Current3539.1.5.1 Power State Parameter Definitions3539.1.5.2 Definition and Measurement Techniques of SC2200 Current Parameters3539.1.5.3 Definition of System Conditions for Measuring On Parameters3549.1.5.4 DC Current Measurements3549.1.6 Ball Capacitance and Inductance3569.1.7 Pull-Up and Pull-Down Resistors3579.2 DC Characteristics3589.2.1 INAB DC Characteristics3599.2.2 INBTN DC Characteristics3599.2.3 INPCI DC Characteristics3599.2.4 INSTRP DC Characteristics3609.2.5 INT DC Characteristics3609.2.6 INTS DC Characteristics3609.2.7 INTS1 DC Characteristics3609.2.8 INUSB DC Characteristics3619.2.9 OAC97 DC Characteristics3619.2.10 ODn DC Characteristics3619.2.11 ODPCI DC Characteristics3629.2.12 Op/n DC Characteristics3629.2.13 OPCI DC Characteristics3629.2.14 OUSB DC Characteristics3629.2.15 TSp/n DC Characteristics3629.2.15.1 Exceptions3629.3 AC Characteristics3639.3.1 Memory Controller Interface3649.3.2 Video Port3679.3.3 CRT and TFT Interface3689.3.4 ACCESS.bus Interface3709.3.5 PCI Bus Interface3739.3.5.1 Measurement and Test Conditions3779.3.6 Sub-ISA Interface3799.3.7 LPC Interface3839.3.8 IDE Interface3849.3.9 Universal Serial Bus (USB) Interface4029.3.10 Serial Port (UART)4069.3.11 Fast IR Port4079.3.12 Parallel Port Interface4089.3.12.1 Extended Capabilities Port (ECP)4109.3.13 Audio Interface (AC97)4129.3.14 Power Management4179.3.15 Power-Up Sequencing4189.3.16 JTAG Interface420Package Specifications42310.1 Thermal Characteristics42310.1.1 Heatsink Considerations42410.2 Physical Dimensions425Support Documentation427A.1 Order Information427A.2 Data Book Revision History428Size: 3.28 MBPages: 429Language: EnglishOpen manual