Bosch TTCAN User Manuals

Table of Contents

• 1. About this Document

  6
  • 1.1 Change Control

    6
    • 1.1.1 Current Status

      6
    • 1.1.2 Change History

      6
  • 1.2 Conventions

    6
  • 1.3 Scope

    6
  • 1.4 References

    6
  • 1.5 Terms and Abbreviations

    7
• 2. Functional Description

  8
  • 2.1 Functional Overview

    8
  • 2.2 Block Diagram

    9
  • 2.3 Operating Modes

    10
    • 2.3.1 Software Initialisation

      10
    • 2.3.2 CAN Message Transfer

      10
    • 2.3.3 Disabled Automatic Retransmission

      11
    • 2.3.4 Test Mode

      11
      • 2.3.4.1 Test Register (addresses 0x0B & 0x0A)

        11
      • 2.3.4.2 Disable Watchdog Mode

        12
      • 2.3.4.3 Silent Mode

        12
      • 2.3.4.4 Loop Back Mode

        13
      • 2.3.4.5 Loop Back combined with Silent Mode

        13
      • 2.3.4.6 Software control of Pin CAN_TX

        14
      • 2.3.4.7 No Message RAM Mode

        14
• 3. Programmer’s Model

  15
  • 3.1 Hardware Reset Description

    16
  • 3.2 CAN Protocol Related Registers

    17
    • 3.2.1 CAN Control Register (addresses 0x01 & 0x00)

      17
    • 3.2.2 Status Register (addresses 0x03 & 0x02)

      18
      • 3.2.2.1 Status Interrupts

        19
    • 3.2.3 Error Counter (addresses 0x05 & 0x04)

      19
    • 3.2.4 Bit Timing Register (addresses 0x07 & 0x06)

      19
    • 3.2.5 BRP Extension Register (addresses 0x0D & 0x0C)

      20
  • 3.3 Message Interface Register Sets

    20
    • 3.3.1 IFx Command Mask Registers

      21
      • 3.3.1.1 Direction = Write

        21
      • 3.3.1.2 Direction = Read

        22
    • 3.3.2 IFx Command Request Registers

      22
    • 3.3.3 IFx Message Buffer Registers

      23
      • 3.3.3.1 IFx Mask Registers

        23
      • 3.3.3.2 IFx Arbitration Registers

        23
      • 3.3.3.3 IFx Message Control Registers

        24
      • 3.3.3.4 IFx Data A and Data B Registers

        24
    • 3.3.4 Message Object in the Message Memory

      24
  • 3.4 Message Handler Registers

    27
    • 3.4.1 Interrupt Register (addresses 0x09 & 0x08)

      27
    • 3.4.2 Transmission Request Registers

      28
    • 3.4.3 New Data Registers

      28
    • 3.4.4 Interrupt Pending Registers

      28
    • 3.4.5 Message Valid 1 Register

      29
  • 3.5 Registers for Time Triggered Communication

    29
    • 3.5.1 Trigger Memory Access Register (addresses 0x0F & 0x0E)

      29
    • 3.5.2 IF1 Data B1 and B2 Registers for Trigger Memory Access

      29
    • 3.5.3 TT Operation Mode Register (addresses 0x29 & 0x28)

      30
    • 3.5.4 TT Matrix Limits1 Register (addresses 0x2B & 0x2A)

      31
    • 3.5.5 TT Matrix Limits2 Register (addresses 0x2D & 0x2C)

      31
    • 3.5.6 TT Application Watchdog Limit Register (addresses 0x2F & 0x2E)

      32
    • 3.5.7 TT Interrupt Enable Register (addresses 0x31 & 0x30)

      32
    • 3.5.8 TT Interrupt Vector Register (addresses 0x33 & 0x32)

      32
    • 3.5.9 TT Global Time Register (addresses 0x35 & 0x34)

      34
    • 3.5.10 TT Cycle Time Register (addresses 0x37 & 0x36)

      34
    • 3.5.11 TT Local Time Register (addresses 0x39 & 0x38)

      34
    • 3.5.12 TT Master State Register (addresses 0x3B & 0x3A)

      34
    • 3.5.13 TT Cycle Count Register (addresses 0x3D & 0x3C)

      35
    • 3.5.14 TT Error Level Register (addresses 0x3F & 0x3E)

      35
    • 3.5.15 TUR Numerator Configuration Low Register (addresses 0x57 & 0x56)

      35
    • 3.5.16 TUR Denominator Configuration Register (addresses 0x59 & 0x58)

      36
    • 3.5.17 TUR Numerator Actual Registers (addresses 0x5B & 0x5A)

      36
    • 3.5.18 TT Stop_Watch Register (addresses 0x61 & 0x60)

      36
    • 3.5.19 TT Global Time Preset Register (addresses 0x65 & 0x64)

      37
    • 3.5.20 TT Clock Control Register (addresses 0x67 & 0x66)

      37
    • 3.5.21 TT Sync_Mark Register (addresses 0x69 & 0x68)

      38
    • 3.5.22 TT Time Mark Register (addresses 0x6D & 0x6C)

      39
    • 3.5.23 TT Gap Control Register (addresses 0x6F & 0x6E)

      39
• 4. CAN Application

  41
  • 4.1 Internal CAN Message Handling

    41
    • 4.1.1 Data Transfer Between IFx Registers and Message RAM

      41
    • 4.1.2 Transmission of Messages in Event Driven CAN Communication

      42
    • 4.1.3 Acceptance Filtering of Received Messages

      43
      • 4.1.3.1 Reception of Data Frame

        43
      • 4.1.3.2 Reception of Remote Frame

        43
    • 4.1.4 Storing Received Messages in FIFO Buffers

      43
    • 4.1.5 Receive / Transmit Priority

      44
  • 4.2 Configuration of the Module

    44
    • 4.2.1 Configuration of the Bit Timing

      45
      • 4.2.1.1 Bit Time and Bit Rate

        45
      • 4.2.1.2 Propagation Time Segment

        46
      • 4.2.1.3 Phase Buffer Segments and Synchronisation

        47
      • 4.2.1.4 Oscillator Tolerance Range

        50
      • 4.2.1.5 Configuration of the CAN Protocol Controller

        50
      • 4.2.1.6 Calculation of the Bit Timing Parameters

        51
      • 4.2.1.7 Example for Bit Timing at high Baudrate

        52
      • 4.2.1.8 Example for Bit Timing at low Baudrate

        53
    • 4.2.2 Configuration of the Message Memory

      53
      • 4.2.2.1 Configuration of a Transmit Object for Data Frames

        54
      • 4.2.2.2 Configuration of a Single Receive Object for Data Frames

        54
      • 4.2.2.3 Configuration of a FIFO Buffer

        55
      • 4.2.2.4 Configuration of a Single Receive Object for Remote Frames

        55
  • 4.3 CAN Communication

    56
    • 4.3.1 Handling of Interrupts

      56
    • 4.3.2 Updating a Transmit Object

      57
    • 4.3.3 Changing a Transmit Object

      58
    • 4.3.4 Reading Received Messages

      58
    • 4.3.5 Requesting New Data for a Receive Object

      58
    • 4.3.6 Reading from a FIFO Buffer

      58
• 5. TTCAN Application

  60
  • 5.1 TTCAN Configuration

    60
    • 5.1.1 TTCAN Timing

      60
    • 5.1.2 Message Scheduling

      61
    • 5.1.3 Trigger Memory

      62
    • 5.1.4 Message Objects

      64
      • 5.1.4.1 Reference Message

        64
      • 5.1.4.2 Periodic Transmit Message

        64
      • 5.1.4.3 Event Driven Transmit Message

        65
  • 5.2 TTCAN Schedule Initialisation

    65
    • 5.2.1 Time Slaves

      65
    • 5.2.2 Potential Time Masters

      65
  • 5.3 TTCAN Message Handling

    66
    • 5.3.1 Message Reception

      66
    • 5.3.2 Message Transmission

      66
      • 5.3.2.1 Periodic Messages

        66
      • 5.3.2.2 Event Driven Messages

        66
  • 5.4 TTCAN Gap Control

    67
  • 5.5 Stopwatch

    67
  • 5.6 Local Time, Cycle Time, and Global Time and External Clock Synchronisation

    67
  • 5.7 TTCAN Interrupt and Error Handling

    69
  • 5.8 Configuration Example

    70
• 6. CPU Interface

  75
  • 6.1 Customer Interface

    75
  • 6.2 Timing of the WAIT output signal

    76
  • 6.3 Interrupt Timing

    76
• 7. Appendix

  77
  • 7.1 List of Figures

    77