User ManualTable of ContentsCopyright information2Overview3Summary of USBS63Feature list3Included in delivery3Hardware4Block Diagram4Spartan-6TM FPGA4Powering USBS66Configuration7USB2.0 controller8External memory9Peripherals11External expansion connectors13FPGA design17Cypress FX-2 LP and USB basics17Clocking FPGA designs17FX-2/FPGA slave FIFO connection18Introduction to example FPGA designs18FPGA source code copyright information20FPGA source code license20Disclaimer of warranty20Design “usbs6_soc”21Files and modules21src/wishbone_pkg.vhd:21src/usbs6_soc_top.vhd:22src/wb_intercon.vhd:22src/wb_ma_fx2.vhd:22src/wb_sl_bram.vhd:22src/wb_sl_gpio.vhd:22src/wb_sl_flash.vhd:22src/wb_sl_mcb.vhd:23src/wb_sl_uart.vhd:23src/xil_uart_macro/:23src/xil_mcb_mig/:23src/fx2_slfifo_ctrl.vhd:23src/sync_fifo.vhd:25src/sfifo_hd_a1Kx18b0K5x36.vhd:25src/flash_ctrl.vhd:25usbs6_soc.xise:25usbs6_soc.ucf:25usbs6_soc_fpga_consts.h:25Software Pseudo-Code Example:25WISHBONE transactions25WISHBONE signals driven by the master:26WISHBONE signals driven by slaves:26Example:27Design “usbs6_bram”27Files and modules28src/wishbone_pkg.vhd:28src/usbs6_bram_top.vhd:28src/wb_ma_fx2.vhd:28src/wb_sl_bram.vhd:28src/sim_tb/wb_sl_bram_tb.vhd:28src/fx2_slfifo_ctrl.vhd:28src/sync_fifo.vhd:28usbs6_bram.xise:28usbs6_bram.ucf:28wb_sl_bram_tb.do:28wb_sl_bram_tb.cmd:29Software30Introduction30Changes to previous versions30Windows31Requirements31Driver installation31Build UDK31Prerequisites31Solution creation and build31Linux33Requirements33Drivers33USB33PCI34Build UDK35Prerequisites35Makefile creation and build35Use APIs in own projects37C++ API37Add project to UDK build37C API37.NET API38API Functions in detail38API Error handling38C++ and .NET API38C API38Methods/Functions39Device enumeration40Methods/Functions40Information gathering43Methods/Functions43Using devices45Methods/Functions45UDKLab50Introduction50The main screen51Using UDKLab52FPGA configuration53FPGA design flashing54Projects54Initializing sequence55Content panel57Additional information60Using SPI-Flash for configuration60How to store configuration data in SPI-Flash60Loading SPI-Flash via USB60SPI-Flash Indirect Programming Using FPGA JTAG Chain60SPI-Flash Direct Programming using iMPACT60IO pairing and etch length report62J3 VG-96 pin connector - Differential pairs (28 IN, 12 IN/OUT )62J4 IDC-50 pin connector - Differential pairs (17 IN/OUT)65Mechanical dimensions68Table of contents69Size: 1.73 MBPages: 71Language: EnglishOpen manual