User ManualTable of ContentsContents5Preface15About this document15Intended audience15Using this manual15Typographical conventions16Product revision status16Timing diagram conventions17Further reading17ARM publications17Other publications171 Introduction211.1 About the ARM720T processor211.1.1 EmbeddedICE-RT logic23Changes to the programmer’s model241.2 Coprocessors251.3 About the instruction set251.3.1 Format summary261.3.2 ARM instruction set271.3.3 Thumb instruction set341.4 Silicon revisions382 Programmer’s Model412.1 Processor operating states412.1.1 Switching between processor states41Entering Thumb state41Entering ARM state412.2 Memory formats422.2.1 Big-endian format422.2.2 Little-endian format432.3 Instruction length432.4 Data types432.5 Operating modes442.5.1 Changing operating modes442.6 Registers442.6.1 The ARM state register set44Interrupt modes452.6.2 The Thumb state register set462.6.3 The relationship between ARM and Thumb state registers472.6.4 Accessing high registers in Thumb state472.7 Program status registers482.7.1 The condition code flags482.7.2 The control bits482.7.3 Reserved bits492.8 Exceptions502.8.1 Action on entering an exception502.8.2 Action on leaving an exception512.8.3 Exception entry and exit summary512.8.4 Fast interrupt request522.8.5 Interrupt request522.8.6 Abort522.8.7 Software interrupt532.8.8 Undefined instruction532.8.9 Exception vectors532.8.10 Exception priorities542.8.11 Exception restrictions542.9 Relocation of low virtual addresses by the FCSE PID552.10 Reset562.11 Implementation-defined behavior of instructions572.11.1 Indexed addressing on a Data Abort572.11.2 Early termination573 Configuration613.1 About configuration613.1.1 Compatibility613.1.2 Notation613.2 Internal coprocessor instructions623.3 Registers633.3.1 ID Register633.3.2 Control Register64Enabling the MMU653.3.3 Translation Table Base Register653.3.4 Domain Access Control Register663.3.5 Fault Status Register663.3.6 Fault Address Register673.3.7 Cache Operations Register673.3.8 TLB Operations Register673.3.9 Process Identifier Registers68Fast Context Switch Extension Process Identifier Register68Changing FCSE PID68Trace Process Identifier Register683.3.10 Register 14, reserved693.3.11 Test Register694 Instruction and Data Cache734.1 About the instruction and data cache734.1.1 IDC operation734.1.2 Cachable bit73Cachable reads (C=1)73Uncachable reads (C=0)734.1.3 Read-lock-write744.2 IDC validity744.2.1 Software IDC flush744.2.2 Doubly-mapped space744.3 IDC enable, disable, and reset745 Write Buffer775.1 About the write buffer775.1.1 Bufferable bit775.2 Write buffer operation785.2.1 Bufferable write785.2.2 Unbufferable write785.2.3 Read-lock-write785.2.4 Reading from a noncachable area785.2.5 Draining the write buffer785.2.6 Multi-word writes786 The Bus Interface816.1 About the bus interface816.1.1 Summary of the AHB transfer mechanism816.2 Bus interface signals836.3 Transfer types856.4 Address and control signals876.4.1 HADDR[31:0]876.4.2 HWRITE876.4.3 HSIZE[2:0]876.4.4 HBURST[2:0]886.4.5 HPROT[3:0]886.5 Slave transfer response signals896.5.1 HREADY896.5.2 HRESP[1:0]906.6 Data buses906.6.1 HWDATA[31:0]906.6.2 HRDATA[31:0]916.6.3 Endianness916.7 Arbitration926.7.1 HBUSREQ926.7.2 HLOCK926.7.3 HGRANT926.8 Bus clocking936.8.1 HCLK936.8.2 HCLKEN936.9 Reset937 Memory Management Unit977.1 About the MMU977.1.1 Access permissions and domains987.1.2 Translated entries987.2 MMU program-accessible registers997.3 Address translation1007.3.1 Translation Table Base Register1007.3.2 Level one fetch1027.3.3 Level one descriptor1027.3.4 Section descriptor1047.3.5 Coarse page table descriptor1047.3.6 Fine page table descriptor1057.3.7 Translating section references1067.3.8 Level two descriptor1067.3.9 Translating large page references1087.3.10 Translating small page references1097.3.11 Translating tiny page references1107.3.12 Subpages1107.4 MMU faults and CPU aborts1117.5 Fault address and fault status registers1127.5.1 Fault Status1127.6 Domain access control1137.7 Fault checking sequence1157.7.1 Alignment fault1157.7.2 Translation fault1167.7.3 Domain fault1167.7.4 Permission fault1167.8 External aborts1177.9 Interaction of the MMU and cache1177.9.1 Enabling the MMU1177.9.2 Disabling the MMU1178 Coprocessor Interface1218.1 About coprocessors1218.1.1 Coprocessor availability1228.2 Coprocessor interface signals1238.3 Pipeline-following signals1248.4 Coprocessor interface handshaking1258.4.1 The coprocessor1258.4.2 The ARM720T core1258.4.3 Coprocessor signaling1268.4.4 Consequences of busywaiting1268.4.5 Coprocessor register transfer instructions1278.4.6 Coprocessor data operations1278.4.7 Coprocessor load and store operations1288.5 Connecting coprocessors1298.5.1 Connecting a single coprocessor1298.5.2 Connecting multiple coprocessors1298.6 Not using an external coprocessor1308.7 STC operations1308.8 Undefined instructions1308.9 Privileged instructions1309 Debugging Your System1339.1 About debugging your system1349.1.1 A typical debug system1349.2 Controlling debugging1359.2.1 Debug modes1369.2.2 Examining system state during debugging1369.3 Entry into debug state1379.3.1 Entry into debug state on breakpoint1389.3.2 Entry into debug state on watchpoint1389.3.3 Entry into debug state on debug request1399.3.4 Action of the ARM720T processor in debug state1399.3.5 Clocks1409.4 Debug interface1419.4.1 Debug interface signals1419.5 ARM720T core clock domains1419.6 The EmbeddedICE-RT macrocell1429.7 Disabling EmbeddedICE-RT1439.8 EmbeddedICE-RT register map1449.9 Monitor mode debugging1449.9.1 Enabling monitor mode1449.9.2 Restrictions on monitor-mode debugging1459.10 The debug communications channel1469.10.1 Domain Access Control Register146Instructions1479.10.2 Communications through the DCC148Sending a message to the debugger148Receiving a message from the debugger1489.11 Scan chains and the JTAG interface1499.11.1 Scan chain implementation149Scan chain 1149Scan chain 2149Scan chain 151509.11.2 Controlling the JTAG interface1509.12 The TAP controller1519.12.1 Resetting the TAP controller1519.13 Public JTAG instructions1529.13.1 SCAN_N (b0010)1529.13.2 INTEST (b1100)1529.13.3 IDCODE (b1110)1539.13.4 BYPASS (b1111)1539.13.5 RESTART (b0100)1539.14 Test data registers1549.14.1 Bypass register1549.14.2 ARM720T processor device identification (ID) code register1549.14.3 Instruction register1559.14.4 Scan path select register1559.14.5 Scan chains 1 and 2156Scan chain 1156Scan chain 21569.15 Scan timing1579.15.1 Scan chain 1 cells1579.16 Examining the core and the system in debug state1589.16.1 Determining the core state1599.16.2 Determining system state1609.17 Exit from debug state1619.18 The program counter during debug1629.18.1 Breakpoints1629.18.2 Watchpoints1629.18.3 Watchpoint with another exception1639.18.4 Debug request1639.18.5 System speed access1639.18.6 Summary of return address calculations1649.19 Priorities and exceptions1649.19.1 Breakpoint with Prefetch Abort1649.19.2 Interrupts1659.19.3 Data Aborts1659.20 Watchpoint unit registers1659.20.1 Programming and reading watchpoint registers1659.20.2 Using the data, and address mask registers1679.20.3 The watchpoint unit control registers1679.21 Programming breakpoints1689.21.1 Hardware breakpoints1689.21.2 Software breakpoints169Setting the breakpoint169Clearing the breakpoint1699.22 Programming watchpoints1709.23 Abort status register1709.24 Debug control register1719.24.1 Disabling interrupts1729.24.2 Forcing DBGRQ1729.24.3 Forcing DBGACK1729.25 Debug status register1739.26 Coupling breakpoints and watchpoints1759.26.1 Breakpoint and watchpoint coupling example175CHAINOUT signal1759.26.2 DBGRNG signal1769.27 EmbeddedICE-RT timing17610 ETM Interface17910.1 About the ETM interface17910.2 Enabling and disabling the ETM7 interface17910.3 Connections between the ETM7 macrocell and the ARM720T processor18010.4 Clocks and resets18110.5 Debug request wiring18110.6 TAP interface wiring18111 Test Support18511.1 About the ARM720T test registers18511.2 Automatic Test Pattern Generation (ATPG)18611.2.1 ARM720T processor INTEST/EXTEST wrapper186ATPG18611.3 Test State Register18711.4 Cache test registers and operations18711.4.1 Addressing the CAM and RAM19011.5 MMU test registers and operations19211.5.1 Addressing the CAM, RAM1, and RAM2196A.1 AMBA interface signals201A.2 Coprocessor interface signals202A.3 JTAG and test signals203A.4 Debugger signals204A.5 Embedded trace macrocell interface signals205A.6 ATPG test signals207A.7 Miscellaneous signals207Appendix A Signal Descriptions201Glossary211Index219Size: 1.46 MBPages: 224Language: EnglishOpen manual