Epson S1D13504 User Manuals

Table of Contents

• S1D13504 TECHNICAL MANUAL

  1
  • Customer Support Information

    3
    • Comprehensive Support Tools

      3
    • Evaluation / Demonstration Board

      3
    • Chip Documentation

      3
    • Software

      3
    • Application Engineering Support

      3
• Product Brief

  5
  • Description

    5
  • Features

    5
    • Memory Interface

      5
    • CPU Interface

      5
    • Display Support

      5
    • Display Modes

      5
    • Clock Source

      5
    • Power Down Modes

      5
    • General Purpose IO pins

      5
    • Operating Voltage

      5
    • Package

      5
  • System Block Diagram

    6
• Hardware Functional Specification

  7
  • Table of Contents

    9
  • List of Tables

    13
  • List of Figures

    15
  • 1 Introduction

    17
    • 1.1 Scope

      17
    • 1.2 Overview Description

      17
  • 2 Features

    18
    • 2.1 Memory Interface

      18
    • 2.2 CPU Interface

      18
    • 2.3 Display Support

      18
    • 2.4 Display Modes

      19
    • 2.5 Clock Source

      19
    • 2.6 Miscellaneous

      19
    • 2.7 Package and Pin

      19
      • Table 21: S1D13504 Series Package list

        19
  • 3 Typical System Implementation Diagrams

    20
    • Figure 31: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM

      20
    • Figure 32: Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)

      21
    • Figure 33: Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)

      21
    • Figure 34: Typical System Diagram – Generic Bus, 1Mx16 FPM/EDO-DRAM

      22
  • 4 Block Description

    23
    • 4.1 Functional Block Diagram

      23
      • Figure 41: System Block Diagram Showing Datapaths

        23
    • 4.2 Functional Block Descriptions

      23
      • 4.2.1 Host Interface

        23
      • 4.2.2 Memory Controller

        23
      • 4.2.3 Display FIFO

        23
      • 4.2.4 Look-Up Table

        24
      • 4.2.5 LCD Interface

        24
      • 4.2.6 Power Save

        24
  • 5 Pin Out

    25
    • 5.1 Pinout Diagram for S1D13504F00A

      25
      • Figure 51: Pinout Diagram of F00A

        25
    • 5.2 Pinout Diagram for S1D13504F01A

      26
      • Figure 52: Pinout Diagram of F01A

        26
    • 5.3 Pinout Diagram for S1D13504F02A

      27
      • Figure 53: Pinout Diagram of F02A

        27
    • 5.4 Pin Description

      28
      • 5.4.1 Host Interface

        28
        • Table 51: Host Interface Pin Descriptions 

          28
      • 5.4.2 Memory Interface

        31
        • Table 52: Memory Interface Pin Descriptions 

          31
      • 5.4.3 LCD Interface

        33
        • Table 53: LCD Interface Pin Descriptions 

          33
      • 5.4.4 Clock Input

        33
        • Table 54: Clock Input Pin Description 

          33
      • 5.4.5 CRT and External RAMDAC Interface

        34
        • Table 55: CRT and RAMDAC Interface Pin Descriptions 

          34
      • 5.4.6 Miscellaneous

        36
        • Table 56: Miscellaneous Pin Descriptions 

          36
      • 5.4.7 Power Supply

        36
        • Table 57: Power Supply Pin Descriptions 

          36
    • 5.5 Summary of Configuration Options

      37
      • Table 58: Summary of Power On / Reset Options

        37
    • 5.6 Multiple Function Pin Mapping

      38
      • Table 59: Host Bus Interface Pin Mapping

        38
      • Table 510: Memory Interface Pin Mapping

        38
      • Table 511: LCD, CRT, RAMDAC Interface Pin Mapping

        39
  • 6 D.C. Characteristics

    40
    • Table 61: Absolute Maximum Ratings

      40
    • Table 62: Recommended Operating Conditions

      40
    • Table 63: Input Specifications

      40
    • Table 64: Output Specifications

      41
  • 7 A.C. Characteristics

    42
    • 7.1 CPU Interface Timing

      42
      • 7.1.1 SH-3 Interface Timing

        42
        • Figure 71: SH-3 Interface Timing

          42
        • Table 71: SH-3 Interface Timing

          43
      • 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000)

        44
        • Figure 72: MC68K Bus 1 Interface Timing

          44
        • Table 72: MC68K Bus 1 Interface Timing

          45
      • 7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030)

        46
        • Figure 73: MC68K Bus 2 Interface Timing

          46
        • Table 73: MC68K Bus 2 Interface Timing

          47
      • 7.1.4 Generic MPU Interface Synchronous Timing

        48
        • Figure 74: Generic MPU Interface Synchronous Timing

          48
        • Table 74: Generic MPU Interface Synchronous Timing

          49
      • 7.1.5 Generic MPU Interface Asynchronous Timing

        50
        • Figure 75: Generic MPU Interface Asynchronous Timing

          50
        • Table 75: Generic MPU Interface Asynchronous Timing

          51
    • 7.2 Clock Input Requirements

      52
      • Figure 76: Clock Input Requirements

        52
      • Table 76: Clock Input Requirements

        52
    • 7.3 Memory Interface Timing

      53
      • 7.3.1 EDO-DRAM Read Timing

        53
        • Figure 77: EDO-DRAM Read Timing

          53
        • Table 77: EDO DRAM Read Timing

          54
      • 7.3.2 EDO-DRAM Write Timing

        55
        • Figure 78: EDO-DRAM Write Timing

          55
        • Table 78: EDO DRAM Write Timing

          56
      • 7.3.3 EDO-DRAM Read-Write Timing

        57
        • Figure 79: EDO-DRAM Read-Write Timing

          57
        • Table 79: EDO DRAM Read-Write Timing

          58
      • 7.3.4 EDO-DRAM CAS Before RAS Refresh Timing

        59
        • Figure 710: EDO-DRAM CAS Before RAS Refresh Timing

          59
        • Table 710: EDO-DRAM CAS Before RAS Refresh Timing

          59
      • 7.3.5 EDO-DRAM Self-Refresh Timing

        60
        • Figure 711: EDO-DRAM Self-Refresh Timing

          60
        • Table 711: EDO-DRAM Self-Refresh Timing

          60
      • 7.3.6 FPM-DRAM Read Timing

        61
        • Figure 712: FPM-DRAM Read Timing

          61
        • Table 712: FPM DRAM Read Timing

          62
      • 7.3.7 FPM-DRAM Write Timing

        63
        • Figure 713: FPM-DRAM Write Timing

          63
        • Table 713: FPM-DRAM Write Timing

          64
      • 7.3.8 FPM-DRAM Read-Write Timing

        65
        • Figure 714: FPM-DRAM Read-Write Timing

          65
        • Table 714: FPM-DRAM Read-Write Timing

          66
      • 7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing

        67
        • Figure 715: FPM-DRAM CAS# Before RAS# Refresh Timing

          67
        • Table 715: FPM-DRAM CAS# Before RAS# Refresh Timing

          67
      • 7.3.10 FPM-DRAM Self-Refresh Timing

        68
        • Figure 716: FPM-DRAM CBR Self-Refresh Timing

          68
        • Table 716: FPM-DRAM CBR Self-Refresh Timing

          68
    • 7.4 Display Interface

      69
      • 7.4.1 Power-On/Reset Timing

        69
        • Figure 717: LCD Panel Power-On/Reset Timing

          69
        • Table 717: LCD Panel Power-On/Reset Timing

          69
      • 7.4.2 Suspend Timing

        70
        • Figure 718: LCD Panel Suspend Timing

          70
        • Table 718: LCD Panel Suspend Timing

          70
      • 7.4.3 Single Monochrome 4-Bit Panel Timing

        71
        • Figure 719: Single Monochrome 4-Bit Panel Timing

          71
        • Figure 720: Single Monochrome 4-Bit Panel A.C. Timing

          72
        • Table 719: Single Monochrome 4-Bit Panel A.C. Timing

          72
      • 7.4.4 Single Monochrome 8-Bit Panel Timing

        73
        • Figure 721: Single Monochrome 8-Bit Panel Timing

          73
        • Figure 722: Single Monochrome 8-Bit Panel A.C. Timing

          74
        • Table 720: Single Monochrome 8-Bit Panel A.C. Timing

          74
      • 7.4.5 Single Color 4-Bit Panel Timing

        75
        • Figure 723: Single Color 4-Bit Panel Timing

          75
        • Figure 724: Single Color 4-Bit Panel A.C. Timing

          76
        • Table 721: Single Color 4-Bit Panel A.C. Timing

          76
      • 7.4.6 Single Color 8-Bit Panel Timing (Format 1)

        77
        • Figure 725: Single Color 8-Bit Panel Timing (Format 1)

          77
        • Figure 726: Single Color 8-Bit Panel A.C. Timing (Format 1)

          78
        • Table 722: Single Color 8-Bit Panel A.C. Timing (Format 1)

          78
      • 7.4.7 Single Color 8-Bit Panel Timing (Format 2)

        79
        • Figure 727: Single Color 8-Bit Panel Timing (Format 2)

          79
        • Figure 728: Single Color 8-Bit Panel A.C. Timing (Format 2)

          80
        • Table 723: Single Color 8-Bit Panel A.C. Timing (Format 2)

          80
      • 7.4.8 Single Color 16-Bit Panel Timing

        81
        • Figure 729: Single Color 16-Bit Panel Timing

          81
        • Figure 730: Single Color 16-Bit Panel A.C. Timing

          82
        • Table 724: Single Color 16-Bit Panel A.C. Timing

          82
      • 7.4.9 Dual Monochrome 8-Bit Panel Timing

        83
        • Figure 731: Dual Monochrome 8-Bit Panel Timing

          83
        • Figure 732: Dual Monochrome 8-Bit Panel A.C. Timing

          84
        • Table 725: Dual Monochrome 8-Bit Panel A.C. Timing

          84
      • 7.4.10 Dual Color 8-Bit Panel Timing

        85
        • Figure 733: Dual Color 8-Bit Panel Timing

          85
        • Figure 734: Dual Color 8-Bit Panel A.C. Timing

          86
        • Table 726: Dual Color 8-Bit Panel A.C. Timing

          86
      • 7.4.11 Dual Color 16-Bit Panel Timing

        87
        • Figure 735: Dual Color 16-Bit Panel Timing

          87
        • Figure 736: Dual Color 16-Bit Panel A.C. Timing

          88
        • Table 727: Dual Color 16-Bit Panel A.C. Timing

          88
      • 7.4.12 16-Bit TFT Panel Timing

        89
        • Figure 737: 16-Bit TFT Panel Timing

          89
        • Figure 738: TFT A.C. Timing

          90
        • Table 728: TFT A.C. Timing

          91
      • 7.4.13 CRT Timing

        92
        • Figure 739: CRT Timing

          92
        • Figure 740: CRT A.C. Timing

          93
        • Table 729: CRT A.C. Timing

          94
      • 7.4.14 External RAMDAC Read / Write Timing

        95
        • Figure 741: Generic Bus RAMDAC Read / Write Timing

          95
        • Table 730: Generic Bus RAMDAC Read / Write Timing

          95
  • 8 Registers

    96
    • 8.1 Register Mapping

      96
      • Table 81: S1D13504 Addressing

        96
    • 8.2 Register Descriptions

      96
      • 8.2.1 Revision Code Register

        96
      • 8.2.2 Memory Configuration Registers

        97
        • Table 82: DRAM Refresh Rate Selection

          97
      • 8.2.3 Panel/Monitor Configuration Registers

        98
        • Table 83: Panel Data Width Selection

          98
        • Table 84: FPLINE Polarity Selection

          100
        • Table 85: FPFRAME Polarity Selection

          102
      • 8.2.4 Display Configuration Registers

        103
        • Table 86: Simultaneous Display Option Selection

          103
        • Table 87: Number of Bits-Per-Pixel Selection

          104
        • Table 88: Pixel Panning Selection

          107
      • 8.2.5 Clock Configuration Register

        107
        • Table 89: PCLK Divide Selection

          107
      • 8.2.6 Power Save Configuration Registers

        108
        • Table 810: Suspend Refresh Selection

          108
      • 8.2.7 Miscellaneous Registers

        108
        • Table 811: Minimum Memory Timing Selection

          114
        • Table 812: RAS-to-CAS Delay Timing Select

          115
        • Table 813: RAS Precharge Timing Select

          115
        • Table 814: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency

          115
      • 8.2.8 Look-Up Table Registers

        116
        • Table 815: RGB Index Selection

          116
      • 8.2.9 External RAMDAC Control Registers

        118
  • 9 Display Buffer

    120
    • Table 91: S1D13504 Addressing

      120
    • Figure 91: Display Buffer Addressing

      120
    • 9.1 Image Buffer

      121
    • 9.2 Half Frame Buffer

      121
  • 10 Display Configuration

    122
    • 10.1 Display Mode Data Format

      122
      • Figure 101: 1/2/4/8 Bit-Per-Pixel Format Memory Organization

        122
      • Figure 102: 15/16 Bit-Per-Pixel Format Memory Organization

        123
    • 10.2 Image Manipulation

      124
      • Figure 103: Image Manipulation

        124
  • 11 Clocking

    125
    • 11.1 Maximum MCLK: PCLK Ratios

      125
      • Table 111: Maximum PCLK Frequency with EDO-DRAM

        125
      • Table 112: Maximum PCLK Frequency with FPM-DRAM

        125
    • 11.2 Frame Rate Calculation

      126
      • Table 113: Example Frame Rates

        126
  • 12 Look-Up Table Architecture

    128
    • Table 121: Look-Up Table Configurations

      128
    • 12.1 Gray Shade Display Modes

      128
      • Figure 121: 1 Bit-Per-Pixel – 2-Level Gray-Shade Mode Look-Up Table Architecture

        128
      • Figure 122: 2 Bit-Per-Pixel – 4-Level Gray-Shade Mode Look-Up Table Architecture

        129
      • Figure 123: 4 Bit-Per-Pixel – 16-Level Gray-Shade Mode Look-Up Table Architecture

        129
    • 12.2 Color Display Modes

      130
      • Figure 124: 1 Bit-Per-Pixel – 2-Level Color Look-Up Table Architecture

        130
      • Figure 125: 2 Bit-Per-Pixel – 4-Level Color Mode Look-Up Table Architecture

        131
      • Figure 126: 4 Bit-Per-Pixel – 16-Level Color Mode Look-Up Table Architecture

        132
      • Figure 127: 8 Bit-Per-Pixel – 256-Level Color Mode Look-Up Table Architecture

        133
  • 13 Power Save Modes

    134
    • 13.1 Hardware Suspend

      134
    • 13.2 Software Suspend

      134
    • 13.3 Power Save Mode Function Summary

      135
      • Table 131: Power Save Mode Function Summary

        135
    • 13.4 Pin States in Power Save Modes

      135
      • Table 132: Pin States in Power Save Modes

        135
  • 14 Mechanical Data

    136
    • 14.1 QFP15-128 (S1D13504F00A)

      136
      • Figure 141: Mechanical Drawing QFP15-128

        136
    • 14.2 TQFP15-128 (S1D13504F01A)

      137
      • Figure 142: Mechanical Drawing TQFP15-128

        137
    • 14.3 QFP20-144 (S1D13504F02A)

      138
      • Figure 143: Mechanical Drawing QFP20-144

        138
• Programming Notes and Examples

  139
  • Table Of Contents

    141
  • List Of Tables

    143
  • List of Figures

    143
  • 1 Introduction

    145
  • 2 Programming the S1D13504 Registers

    146
    • 2.1 Registers Requiring Special Consideration

      146
      • 2.1.1 REG[01] bit 0 - Memory Type

        146
      • 2.1.2 REG[22] bits 7-2 - Performance Enhancement Register 0

        146
      • 2.1.3 REG[02] bit 1 - Dual/Single Panel Type

        146
      • 2.1.4 REG[1B] bit 0 - Half Frame Buffer Disable

        147
      • 2.1.5 REG[23] Display FIFO:

        147
    • 2.2 Register Initialization

      147
      • 2.2.1 Initialization Sequence

        147
      • 2.2.2 Initialization Example

        148
        • Table 21: Initializing the S1D13504 Registers

          148
      • 2.2.3 Re-Programming Registers

        149
    • 2.3 Disabling the Half Frame Buffer Sequence:

      149
  • 3 Display Buffer

    150
    • 3.1 Display Buffer Location

      150
    • 3.2 Display Buffer Organization

      150
      • 3.2.1 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)

        150
        • Table 31: Pixel Storage for 1 bpp (2 Colors/Gray Shades) in One Byte of Display Buffer

          150
      • 3.2.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)

        150
        • Table 32: Pixel Storage for 2 bpp (4 Colors/Gray Shades) in One Byte of Display Buffer

          150
      • 3.2.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)

        151
        • Table 33: Pixel Storage for 4 bpp (16 Colors/Gray Shades) in One Byte of Display Buffer

          151
      • 3.2.4 Memory Organization for Eight Bit-per-pixel (256 Colors)

        151
        • Table 34: Pixel Storage for 8 bpp (256 Colors) in One Byte of Display Buffer

          151
      • 3.2.5 Memory Organization for 15 Bit-per-pixel (32768 Colors)

        152
        • Table 35: Pixel Storage for 15 bpp (32768 Colors) in Two Bytes of Display Buffer

          152
      • 3.2.6 Memory Organization for 16 Bit-per-pixel (65536 Colors)

        152
        • Table 36: Pixel Storage for 16 bpp (65536 Colors) in Two Bytes of Display Buffer

          152
    • 3.3 Look-Up Table (LUT)

      153
      • 3.3.1 Look-Up Table Registers

        153
      • 3.3.2 Look-Up Table Organization

        155
        • Table 37: Look-Up Table Configurations

          155
        • Table 38: Recommended LUT Values for 1 bpp Color Mode

          156
        • Table 39: Recommended LUT Values for 2 bpp Color Mode

          156
        • Table 310: Recommended LUT Values to Simulate VGA Default 16 Color Palette

          157
        • Table 311: Recommended LUT Values For 8 bpp Color Mode

          157
        • Table 312: Examples of 256 Pixel Colors Using Linear LUT

          158
        • Table 313: Recommended LUT Values for 1 bpp Gray Shades

          158
        • Table 314: Recommended LUT Values for 2 bpp Gray Shades

          159
        • Table 315: Recommended LUT Values for 8 bpp Gray Shade

          159
  • 4 Advanced Techniques

    161
    • 4.1 Virtual Display

      161
      • Figure 41: Viewport Inside a Virtual Display

        161
      • 4.1.1 Registers

        162
      • 4.1.2 Examples

        162
    • 4.2 Panning and Scrolling

      163
      • 4.2.1 Registers

        164
        • Table 41: Number of Pixels Panned Using Start Address

          164
        • Table 42: Active Pixel Pan Bits

          164
      • 4.2.2 Examples

        165
    • 4.3 Split Screen

      166
      • Figure 42: 320x240 Single Panel For Split Screen

        166
      • 4.3.1 Registers

        166
      • 4.3.2 Examples

        167
  • 5 LCD Power Sequencing and Power Save Modes

    168
    • 5.1 Introduction to LCD Power Sequencing

      168
    • 5.2 Introduction to Power Save Modes

      168
    • 5.3 Registers

      168
    • 5.4 Suspend Sequencing

      169
      • 5.4.1 Suspend Enable Sequence

        169
      • 5.4.2 Suspend Disable Sequence

        170
    • 5.5 LCD Enable/Disable Sequencing (Reg[0D] bit 0)

      170
  • 6 CRT Considerations

    171
    • 6.1 Introduction

      171
      • 6.1.1 CRT Only

        171
        • Table 61: RAMDAC Register Mapping for Little/Big-Endian

          171
        • Table 62: Related Register Data for CRT Only

          172
      • 6.1.2 Simultaneous Display

        172
        • Table 63: 8 bpp Recommended RAMDAC palette data for Simultaneous Display

          173
        • Table 64: Related register data for Simultaneous Display

          175
  • 7 Identifying the S1D13504

    176
  • 8 Hardware Abstraction Layer (HAL)

    177
    • 8.1 Introduction

      177
    • 8.2 API for 13504HAL

      177
      • 8.2.1 Initialization

        177
      • 8.2.2 Screen Manipulation

        179
      • 8.2.3 Color Manipulation

        185
      • 8.2.4 Drawing

        188
      • 8.2.5 Register Manipulation

        190
      • 8.2.6 Miscellaneous

        190
  • 9 Sample Code

    192
    • 9.1 Introduction

      192
      • 9.1.1 Sample code using 13504HAL API

        192
      • 9.1.2 Sample code without using 13504HAL API

        193
  • Appendix A Supported Panel Values

    199
    • A.1 Supported Panel Values

      199
      • Table 91: Passive Single Panel

        199
      • Table 92: Passive Dual Panel

        199
      • Table 93: TFT Panel

        200
• Register Summary

  201
  • REG[00h] Revision Code Register 2 R0

    201
  • REG[01h] Memory Configuration Register 1/0 RW

    201
  • REG[02h] Panel Type Register 1/0 RW

    201
  • REG[03h] Mod Rate Register RW

    201
  • REG[04h] Horizontal Display Width Register RW

    201
  • REG[05h] Horizontal Non-Display Period Register RW

    201
  • REG[06h] HRTC/FPLINE Start Position Register RW

    201
  • REG[07h] HRTC/FPLINE Pulse Width Register RW

    201
  • REG[08h] Vertical Display Height Register 0 RW

    201
  • REG[09h] Vertical Display Height Register 1 RW

    201
  • REG[0Ah] Vertical Non-Display Period Register RW

    201
  • REG[0Bh] VRTC/FPFRAME Start Position Register RW

    201
  • REG[0Ch] VRTC/FPFRAME Pulse Width Register RW

    201
  • REG[0Dh] Display Mode Register RW

    201
  • REG[0Eh] Screen 1 Line Compare Register 0 RW

    201
  • REG[0Fh] Screen 1 Line Compare Register 1 RW

    201
  • REG[10h] Screen 1 Display Start Address Register 0 RW

    201
  • REG[11h] Screen 1 Display Start Address Register 1 RW

    201
  • REG[12h] Screen 1 Display Start Address Register 2 RW

    201
  • REG[13h] Screen 2 Display Start Address Register 0 RW

    201
  • REG[14h] Screen 2 Display Start Address Register 1 RW

    201
  • REG[15h] Screen 2 Display Start Address Register 2 RW

    201
  • REG[16h] Memory Address Offset Register 0 RW

    201
  • REG[17h] Memory Address Offset Register 1 RW

    201
  • REG[18h] Pixel Panning Register RW

    201
  • REG[19h] Clock Configuration Register RW

    201
  • REG[1Ah] Power Save Configuration Register RW

    201
  • REG[1Bh] Miscellanious Disable Register RW

    201
  • REG[1Ch] MD Configuration Readback Register 0 RO

    201
  • REG[1Dh] MD Configuration Readback Register 1 RO

    201
  • REG[1Eh] General IO Pins Configuration Register 0 RW

    201
  • REG[1Fh] General IO Pins Configuration Register 1 RW

    201
  • REG[20h] General IO Pins Status / Control Register 0 RW

    201
  • REG[21h] General IO Pins Status / Control Register 1 RW

    201
  • REG[22h] Performance Enhancement Register 0 1/0 RW

    201
  • REG[23h] Performance Enhancement Register 1 RW

    201
  • REG[24h] Look-Up Table Address Register RW

    201
  • REG[26h] Look-Up Table Data Register RW

    201
  • REG[27h] Look-Up Table Bank Select Register RW

    201
  • REG[28h] or REG[29h] 3 RAMDAC Pixel Read Mask Register RW

    201
  • REG[2Ah] or REG[2Bh] 3 RAMDAC Read Mode Address Register RW

    201
  • REG[2Ch] or REG[2Dh] 3 RAMDAC Write Mode Address Register RW

    201
  • REG[2Eh] or REG[2Fh] 3 RAMDAC Palette Data Register RW

    201
• 13504CFG.EXE Configuration Program

  203
  • Table of Contents

    206
  • List of Figures

    208
  • 13504CFG.EXE

    210
  • Program Requirements

    211
    • Installation

      211
    • Usage

      211
  • Script Mode

    212
  • Interactive Mode

    213
    • 13504CFG Menu Bar

      213
      • Figure 1: 13504CFG Menu Bar

        213
      • Viewing 13504CFG Menu Contents

        213
      • Making 13504CFG Menu Selections

        214
        • Figure 2: 13504CFG Open File

          214
      • Files Menu

        215
        • Figure 3: 13504CFG Files Menu

          215
      • View Menu

        216
        • Figure 4: 13504CFG View Menu

          216
        • Figure 5: 13504CFG Current Configuration

          217
        • Figure 6: 13504CFG Advanced Configuration (Partial View of Screen)

          217
      • Device Menu

        218
        • Figure 7: 13504CFG Device Menu

          218
        • Panel

          219
          • Figure 8: 13504CFG Panel Setup

            219
          • Figure 9: 13504CFG Edit Panel Setup

            220
          • Figure 10: 13504CFG Panel Parameter Edit

            220
        • CRT

          221
          • Figure 11: 13504CFG CRT Setup

            221
          • Figure 12: 13504CFG Edit CRT Setup

            222
          • Figure 13: 13504CFG CRT Parameter Edit

            222
        • Advanced Memory

          223
          • Figure 14: 13504CFG Advanced Memory Setup

            223
          • Figure 15: 13504CFG Edit Advanced Memory Setup

            224
          • Figure 16: 13504CFG Memory Parameter Edit

            224
        • Power Management

          225
          • Figure 17: 13504CFG Power Setup

            225
          • Figure 18: 13504CFG Edit Power Setup

            226
          • Figure 19: 13504CFG Power Parameter Edit

            226
        • Lookup Table (LUT)

          227
          • Figure 20: 13504CFG LUT Setup

            227
          • Figure 21: 13504CFG Edit LUT Setup

            228
          • Figure 22: 13504CFG LUT Parameter Edit

            228
        • Setup

          229
          • Figure 23: 13504CFG Setup

            229
          • Figure 24: 13504CFG Setup Parameter Edit For Register Location, Memory Location, and Memory Size.

            230
      • Help Menu

        230
    • Comments

      231
    • Sample Program Messages

      231
• 13504SHOW Demonstration Program

  233
  • 13504SHOW

    235
    • S1D13504 Supported Evaluation Platforms

      235
    • Installation

      235
    • Usage

      236
    • Comments

      236
    • Program Messages

      236
• 13504SPLT Display Utility

  237
  • 13504SPLT

    239
    • S1D13504 Supported Evaluation Platforms

      239
    • Installation

      239
    • Usage

      240
    • 13504SPLT Example

      240
    • Comments

      241
    • Program Messages

      241
• 13504VIRT Display Utility

  243
  • 13504VIRT

    245
    • S1D13504 Supported Evaluation Platforms

      245
    • Installation

      245
    • Usage

      246
    • 13504VIRT Example

      246
    • Comments

      247
    • Program Messages

      247
• 13504PLAY Diagnostic Utility

  249
  • 13504PLAY

    251
    • S1D13504 Supported Evaluation Platforms

      251
    • Installation

      251
    • Usage

      252
    • 13504PLAY Example

      253
    • Scripting

      253
    • Comments

      254
    • Program Messages

      254
• 13504BMP Demonstration Program

  255
  • 13504BMP

    257
    • Installation

      257
    • Usage

      257
    • Comments

      257
    • Program Messages

      258
• 13504PWR Software Suspend Power Sequencing Utility

  259
  • 13504PWR

    261
    • S1D13504 Supported Evaluation Platforms

      261
    • Installation

      261
    • Usage

      262
    • Comments

      262
    • Program Messages

      263
• 13504DCFG Configuration Program

  265
  • Table of Contents

    267
  • List of Figures

    269
  • 13504DCFG

    271
    • Installation

      271
    • Usage

      271
    • 13504DCFG Configuration Tabs

      272
    • General Tab

      273
      • Figure 1: General Tab

        273
    • Memory Tab

      274
      • Figure 2: Memory Tab

        274
    • Clocks Tab

      275
      • Figure 3: Clocks Tab

        275
    • Panel Tab

      277
      • Figure 4: Panel Tab

        277
    • CRT Tab

      279
      • Figure 5: CRT Tab

        279
    • Defaults Tab

      280
      • Figure 6: Defaults Tab

        280
    • Registers Tab

      281
      • Figure 7: Registers Tab

        281
    • Miscellaneous Flags Tab

      282
      • Figure 8: Miscellaneous Flags Tab

        282
    • Saving to a File

      283
    • Comments

      284
• Windows® CE Display Drivers

  285
  • WINDOWS® CE DISPLAY DRIVERS

    287
    • Program Requirements

      287
    • Example Driver Builds

      287
    • Example Installation

      292
    • Comments

      293
• Wind River WindML v2.0 Display Drivers

  295
  • Wind River WindML v2.0 Display Drivers

    297
    • Building a WindML v2.0 Display Driver

      298
      • 1. Create a working directory and unzip the WindML display driver into it.

        298
      • 2. Configure for the target execution model.

        298
      • 3. Build the WindML v2.0 library.

        298
      • 4. Build a boot ROM image.

        298
      • 5. Create a bootable disk (in drive A:).

        298
      • 6. If necessary, generate a new mode0.h configuration file.

        298
      • 7. Open the S1D13504 workspace.

        299
      • 8. Add support for single line comments.

        299
        • a. In the Tornado “Workspace Views” window, click on the “Builds” tab.

          299
        • b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+” next to it. The expan...

          299
        • c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...

          299
      • 9. Compile the VxWorks image.

        299
      • 10. Copy the VxWorks file to the diskette.

        299
      • 11. Start the VxWorks demo.

        299
• Wind River UGL v1.2 Display Drivers

  301
  • Wind River UGL v1.2 Display Drivers

    303
    • Building a UGL v1.2 Display Driver

      304
      • 1. Create a working directory and unzip the UGL display driver into it.

        304
      • 2. Configure for the target execution model.

        304
      • 3. Build a boot ROM image.

        304
      • 4. Create a bootable disk (in drive A:).

        304
      • 5. If necessary, generate a new mode0.h configuration file.

        304
      • 6. Open the S1D13504 workspace.

        305
      • 7. Add support for single line comments.

        305
        • a. In the Tornado “Workspace” window, click on the “Builds” tab.

          305
        • b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+” next to it. The expan...

          305
        • c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...

          305
      • 8. Compile the VxWorks image.

        305
      • 9. Copy the VxWorks file to the diskette.

        305
      • 10. Start the VxWorks demo.

        305
• S5U13504B00C Rev. 1.0 ISA Bus Evaluation Board User Manual

  307
  • Table of Contents

    309
  • List of Tables

    311
  • List of Figures

    311
  • 1 Introduction

    313
    • 1.1 Features

      313
  • 2 Installation and Configuration

    314
    • Table 21: Configuration DIP Switch Settings

      314
    • Table 22: Host Bus Selection

      314
    • Table 23: Jumper Settings

      314
  • 3 LCD / RAMDAC Interface Pin Mapping

    315
    • Table 31: LCD Signal Connector (J6)

      315
  • 4 CPU / BUS Interface Connector Pinouts

    316
    • Table 41: CPU/BUS Connector (H1) Pinout

      316
    • Table 42: CPU/BUS Connector (H2) Pinout

      317
  • 5 Host Bus Interface Pin Mapping

    318
    • Table 51: Host Bus Interface Pin Mapping

      318
  • 6 Technical Description

    319
    • 6.1 ISA Bus Support

      319
    • 6.2 Non-ISA Bus Support

      320
    • 6.3 DRAM Support

      320
    • 6.4 Decode Logic

      320
    • 6.5 Clock Input Support

      320
    • 6.6 Monochrome LCD Panel Support

      321
    • 6.7 Color Passive LCD Panel Support

      321
    • 6.8 Color TFT LCD Panel Support

      321
    • 6.9 External CMOS RAMDAC Support

      321
    • 6.10 Power Save Modes

      322
    • 6.11 Core VDD Power Supply

      322
    • 6.12 IO VDD Power Supply

      322
    • 6.13 Adjustable LCD Panel Negative Power Supply

      322
    • 6.14 Adjustable LCD Panel Positive Power Supply

      322
    • 6.15 CPU/Bus Interface Header Strips

      323
    • 6.16 Schematic Notes

      323
  • 7 Parts List

    324
  • 8 Schematic Diagrams

    326
    • Figure 1: S1D13504B00C Schematic Diagram (1 of 6)

      326
    • Figure 2: S1D13504B00C Schematic Diagram (2 of 6)

      327
    • Figure 3: S1D13504B00C Schematic Diagram (3 of 6)

      328
    • Figure 4: S1D13504B00C Schematic Diagram (4 of 6)

      329
    • Figure 5: S1D13504B00C Schematic Diagram (5 of 6)

      330
    • Figure 6: S1D13504B00C Schematic Diagram (6 of 6)

      331
• S5U13504-D9000 Evaluation Board User Manual

  333
  • Table of Contents

    335
  • List of Tables

    337
  • List of Figures

    337
  • 1 Introduction

    339
    • Reference

      339
  • 2 Features

    340
    • 2.1 S1D13504 Color Graphics LCD Controller

      340
      • 2.1.1 Display Buffer

        340
      • 2.1.2 LCD Display Support

        341
      • 2.1.3 LCD Interface Pin Mapping

        342
        • Table 21: LCD Connector Pinout

          342
      • 2.1.4 CRT Support

        343
      • 2.1.5 Adjustable LCD BIAS Power Supply

        343
  • 3 D9000 Specifics

    344
    • 3.1 Interface Signals

      344
      • Table 31: Interface Signals

        344
      • 3.1.1 Connector Pinout for Channel A6 and A7

        344
        • Table 32: Connector Pinout for Channel A7 

          344
        • Table 33: Connectors Pinout for Channel A6 

          347
      • 3.1.2 Bus Interface Timing

        349
        • Table 34: DIP Switch Configuration

          349
      • 3.1.3 Memory Address (CS#, M/R#) Decode

        349
      • 3.1.4 Makefpga file

        349
    • 3.2 Board Dimensions

      349
    • 3.3 Support Documentation Notes

      349
    • 3.4 Parts List

      350
    • 3.5 Schematic Diagrams

      351
      • Figure 31: S5U13504-D9000 Schematic Diagram (1 of 4)

        351
      • Figure 32: S5U13504-D9000 Schematic Diagram (2 of 4)

        352
      • Figure 33: S5U13504-D9000 Schematic Diagram (3 of 4)

        353
      • Figure 34: S5U13504-D9000 Schematic Diagram (4 of 4)

        354
      • 3.5.1 PCB Layout

        355
      • 3.5.2 Component Placement

        355
        • Figure 35: Component Placement

          355
      • 3.5.3 Perspective View

        356
        • Figure 36: S5U13504-D9000 Perspective View

          356
• Power Consumption

  357
  • 1 S1D13504 Power Consumption

    359
    • 1.1 Conditions

      360
      • Table 11: S1D13504 Total Power Consumption

        360
  • 2 Summary

    360
• Interfacing to the Philips MIPS PR31500/PR31700 Processor

  361
  • Table of Contents

    363
  • List of Tables

    365
  • List of Figures

    365
  • 1 Introduction

    367
  • 2 Interfacing to the PR31500/PR31700

    368
  • 3 S1D13504 Host Bus Interface

    369
    • 3.1 Generic MPU Host Bus Interface Pin Mapping

      369
      • Table 31: Generic MPU Host Bus Interface Pin Mapping

        369
    • 3.2 Generic MPU Host Bus Interface Signals

      370
  • 4 Direct Connection to the Philips PR31500/PR31700

    371
    • 4.1 Hardware Description

      371
      • Figure 41: Typical Implementation of S1D13504 to PR31500/PR31700 Direct Connection

        371
    • 4.2 Memory Mapping and Aliasing

      372
    • 4.3 S1D13504 Configuration

      373
      • Table 41: S1D13504 Configuration for Direct Connection

        373
      • Table 42: S1D13504 Host Bus Selection for Direct Connection

        373
  • 5 System Design Using the IT8368E PC Card Buffer

    374
    • 5.1 Hardware Description—Using One IT8368E

      374
      • Figure 51: S1D13504 to PR31500/PR31700 Connection using One IT8368E

        375
    • 5.2 Hardware Description—Using Two IT8368E’s

      377
      • Figure 52: S1D13504 to PR31500/PR31700 Connection using Two IT8368E

        377
    • 5.3 IT8368E Configuration

      378
    • 5.4 Memory Mapping and Aliasing

      379
      • Table 51: PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping

        379
      • Table 52: PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E

        379
    • 5.5 S1D13504 Configuration

      380
      • Table 53: S1D13504 Configuration using the IT8368E

        380
      • Table 54: S1D13504 Host Bus Selection using the IT8368E

        380
  • 6 Software

    381
  • 7 References

    382
    • 7.1 Documents

      382
    • 7.2 Document Sources

      382
  • 8 Technical Support

    383
    • 8.1 EPSON LCD/CRT Controllers (S1D13504)

      383
    • 8.2 Philips MIPS PR31500/PR31700 Processor

      383
    • 8.3 ITE IT8368E

      383
• Interfacing to the NEC VR4102™ Microprocessor

  385
  • Table of Contents

    387
  • List of Tables

    389
  • List of Figures

    389
  • 1 Introduction

    391
  • 2 Interfacing to the NEC VR4102

    392
    • 2.1 The NEC VR4102 System Bus

      392
      • 2.1.1 Overview

        392
      • 2.1.2 LCD Memory Access Cycles

        393
        • Figure 21: NEC VR4102 Read/Write Cycles

          393
  • 3 S1D13504 Host Bus Interface

    394
    • 3.1 Generic MPU Host Bus Interface Pin Mapping

      394
      • Table 31: Generic MPU Host Bus Interface Pin Mapping

        394
    • 3.2 Generic MPU Host Bus Interface Signals

      395
  • 4 VR4102 to S1D13504 Interface

    396
    • 4.1 Hardware Description

      396
      • Figure 41: Typical Implementation of VR4102 to S1D13504 Interface

        396
    • 4.2 S1D13504 Hardware Configuration

      397
      • Table 41: Summary of Power-On/Reset Options

        397
      • Table 42: Host Bus Interface Selection

        397
    • 4.3 NEC VR4102™ Configuration

      398
      • Table 42: NEC/S1D13504 Truth Table

        398
  • 5 Software

    399
  • 6 References

    400
    • 6.1 Documents

      400
    • 6.2 Document Sources

      400
  • 7 Technical Support

    401
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)

      401
    • 7.2 NEC Electronics Inc. (VR4102).

      401
• Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor

  403
  • Table of Contents

    405
  • List of Tables

    407
  • List of Figures

    407
  • 1 Introduction

    409
  • 2 Interfacing to the MCF5307

    410
    • 2.1 The MCF5307 System Bus

      410
      • 2.1.1 Overview

        410
      • 2.1.2 Normal (Non-Burst) Bus Transactions

        410
        • Figure 21: MCF5307 Memory Read Cycle

          411
        • Figure 22: MCF5307 Memory Write Cycle

          411
      • 2.1.3 Burst Cycles

        412
    • 2.2 Chip-Select Module

      412
  • 3 S1D13504 Bus Interface

    413
    • 3.1 Generic MPU Host Bus Interface Pin Mapping

      413
      • Table 31: Generic MPU Host Bus Interface Pin Mapping

        413
    • 3.2 Generic MPU Host Bus Interface Signals

      414
  • 4 MCF5307 To S1D13504 Interface

    415
    • 4.1 Hardware Connections

      415
      • Figure 41: Typical Implementation of MCF5307 to S1D13504 Interface

        415
    • 4.2 S1D13504 Hardware Configuration

      416
      • Table 41: S1D13504 Configuration Settings

        416
      • Table 42: S1D13504 Host Bus Selection

        416
    • 4.3 Memory/Register Mapping

      417
    • 4.4 MCF5307 Chip Select Configuration

      417
  • 5 Software

    418
  • 6 References

    419
    • 6.1 Documents

      419
    • 6.2 Document Sources

      419
  • 7 Technical Support

    420
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)

      420
    • 7.2 Motorola MCF5307 Processor

      420
• Interfacing to the Motorola MC68328 "Dragonball" Microprocessor

  421
  • Document Number: X19A-G-013-02

    421
  • Table of Contents

    423
  • List of Tables

    425
  • List of Figures

    425
  • 1 Introduction

    427
  • 2 Interfacing to the MC68328

    428
    • 2.1 The 68328 System Bus

      428
    • 2.2 Chip-Select Module

      428
  • 3 S1D13504 Host Bus Interface

    429
    • 3.1 Generic MPU Host Bus Interface Pin Mapping

      429
      • Table 31: Generic MPU Host Bus Interface Pin Mapping

        429
    • 3.2 Generic MPU Host Bus Interface Signals

      430
  • 4 MC68328 To S1D13504 Interface

    431
    • 4.1 Hardware Description

      431
      • Figure 41: Block Diagram of MC68328 to S1D13504 Interface - MC68000 Bus 1 Interface Mode

        431
      • Figure 42: Block Diagram of MC68328 to S1D13504 Interface - Generic Interface Mode

        432
    • 4.2 S1D13504 Hardware Configuration

      433
      • Table 41: Summary of Power-On/Reset Options

        433
      • Table 42: S1D13504 Host Bus Selection

        433
      • Table 43: Memory Configuration

        434
    • 4.3 MC68328 Chip Select Configuration

      434
  • 5 Software

    435
  • 6 References

    436
    • 6.1 Documents

      436
    • 6.2 Document Sources

      436
  • 7 Technical Support

    437
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)

      437
    • 7.2 Motorola MC68328 Processor

      437
• Interfacing to the Motorola MPC821 Microprocessor

  439
  • Document Number: X19A-G-010-05

    439
  • Table of Contents

    441
  • List of Tables

    443
  • List of Figures

    443
  • 1 Introduction

    445
  • 2 Interfacing to the MPC821

    446
    • 2.1 The MPC8xx System Bus

      446
    • 2.2 MPC821 Bus Overview

      446
      • 2.2.1 Normal (Non-Burst) Bus Transactions

        447
        • Figure 21: Power PC Memory Read Cycle

          447
        • Figure 22: Power PC Memory Write Cycle

          448
    • 2.3 Memory Controller Module

      449
      • 2.3.1 General-Purpose Chip Select Module (GPCM)

        449
      • 2.3.2 User-Programmable Machine (UPM)

        450
  • 3 S1D13504 Host Bus Interface

    451
    • 3.1 Generic MPU Host Bus Interface Pin Mapping

      451
      • Table 31: Generic MPU Host Bus Interface Pin Mapping

        451
    • 3.2 Generic MPU Host Bus Interface Signals

      452
  • 4 MPC821 to S1D13504 Interface

    453
    • 4.1 Hardware Description

      453
      • Figure 41: Typical Implementation of MPC821 to S1D13504 Interface

        453
    • 4.2 Hardware Connections

      454
      • Table 41: List of Connections from MPC821ADS to S1D13504

        454
    • 4.3 S1D13504 Hardware Configuration

      456
      • Table 42: Summary of Power-On/Reset Options

        456
      • Table 42: Host Bus Interface Selection

        456
    • 4.4 Register/Memory Mapping

      457
    • 4.5 MPC821 Chip Select Configuration

      457
    • 4.6 Test Software

      458
      • 4.6.1 Source Code

        458
  • 5 Software

    460
  • 6 References

    461
    • 6.1 Documents

      461
    • 6.2 Document Sources

      461
  • 7 Technical Support

    462
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)

      462
    • 7.2 Motorola MPC821 Processor

      462
• Interfacing to the PC Card Bus

  463
  • Table of Contents

    465
  • List of Tables

    467
  • List of Figures

    467
  • 1 Introduction

    469
  • 2 Interfacing to the PC Card Bus

    470
    • 2.1 The PC Card System Bus

      470
      • 2.1.1 PC Card Overview

        470
      • 2.1.2 Memory Access Cycles

        470
        • Figure 21: PC Card Read Cycle

          471
        • Figure 22: PC Card Write Cycle

          471
  • 3 S1D13504 Host Bus Interface

    472
    • 3.1 Generic MPU Host Bus Interface Pin Mapping

      472
      • Table 31: Generic MPU Host Bus Interface Pin Mapping

        472
    • 3.2 Generic MPU Host Bus Interface Signals

      473
  • 4 PC Card to S1D13504 Interface

    474
    • 4.1 Hardware Description

      474
      • Figure 41: Typical Implementation of PC Card to S1D13504 Interface

        474
    • 4.2 S1D13504 Hardware Configuration

      475
      • Table 41: Summary of Power-On/Reset Options

        475
      • Table 42: Host Bus Interface Selection

        475
    • 4.3 PAL Equations

      476
    • 4.4 Register/Memory Mapping

      476
  • 5 Software

    477
  • 6 References

    478
    • 6.1 Documents

      478
    • 6.2 Document Sources

      478
  • 7 Technical Support

    479
    • 7.1 EPSON LCD/CRT Controllers (S1D13504)

      479
    • 7.2 PC Card Standard

      479
• Interfacing to the Toshiba MIPS TX3912 Processor

  481
  • Table of Contents

    483
  • List of Tables

    485
  • List of Figures

    485
  • 1 Introduction

    487
  • 2 Interfacing to the TX3912

    488
  • 3 S1D13504 Host Bus Interface

    489
    • 3.1 Generic MPU Host Bus Interface Pin Mapping

      489
      • Table 31: Generic MPU Host Bus Interface Pin Mapping

        489
    • 3.2 Generic MPU Host Bus Interface Signals

      490
  • 4 Direct Connection to the Toshiba TX3912

    491
    • 4.1 Hardware Description

      491
      • Figure 41: Typical Implementation of TX3912 to S1D13504 Direct Connection

        491
    • 4.2 Memory Mapping and Aliasing

      492
    • 4.3 S1D13504 Hardware Configuration

      493
      • Table 41: S1D13504 Configuration for Direct Connection

        493
      • Table 42: S1D13504 Host Bus Selection for Direct Connection

        493
  • 5 System Design Using the IT8368E PC Card Buffer

    494
    • 5.1 Hardware Description—Using One IT8368E

      494
      • Figure 51: S1D13504 to TX3912 Connection using One IT8368E

        495
    • 5.2 Hardware Description—Using Two IT8368E’s

      496
      • Figure 52: S1D13504 to TX3912 Connection using Two IT8368E

        497
    • 5.3 IT8368E Configuration

      498
    • 5.4 Memory Mapping and Aliasing

      499
      • Table 51: TX3912 to Unbuffered PC Card Slots System Address Mapping

        499
      • Table 52: TX3912 to PC Card Slots Address Remapping using the IT8368E

        499
    • 5.5 S1D13504 Configuration

      500
      • Table 53: S1D13504 Configuration using the IT8368E

        500
      • Table 54: S1D13504 Host Bus Selection using the IT8368E

        500
  • 6 Software

    501
  • 7 References

    502
    • 7.1 Documents

      502
    • 7.2 Document Sources

      502
  • 8 Technical Support

    503
    • 8.1 EPSON LCD/CRT Controllers (S1D13504)

      503
    • 8.2 Toshiba MIPS TX3912 Processor

      503
    • 8.3 ITE IT8368E

      503