Fujitsu C141-E090-02EN User Manuals

Table of Contents

• Front title

  1
• PREFACE

  4
• CONTENTS

  8
• FIGURES

  12
• TABLES

  14
• CHAPTER 1 DEVICE OVERVIEW

  16
  • 1.1 Features

    16
    • 1.1.1 Functions and performance

      16
    • 1.1.2 Adaptability

      17
    • 1.1.3 Interface

      17
  • 1.2 Device Specifications

    19
    • 1.2.1 Specifications summary

      19
    • 1.2.2 Model and product number

      20
  • 1.3 Power Requirements

    20
  • 1.4 Environmental Specifications

    23
  • 1.5 Acoustic Noise

    23
  • 1.6 Shock and Vibration

    24
  • 1.7 Reliability

    24
  • 1.8 Error Rate

    25
  • 1.9 Media Defects

    25
• CHAPTER 2 DEVICE CONFIGURATION

  26
  • 2.1 Device Configuration

    26
  • 2.2 System Configuration

    28
    • 2.2.1 ATA interface

      28
    • 2.2.2 1 drive connection

      28
    • 2.2.3 2 drives connection

      28
• CHAPTER 3 INSTALLATION CONDITIONS

  30
  • 3.1 Dimensions

    30
  • 3.2 Mounting

    32
  • 3.3 Cable Connections

    36
    • 3.3.1 Device connector

      36
    • 3.3.2 Cable connector specifications

      37
    • 3.3.3 Device connection

      37
    • 3.3.4 Power supply connector (CN1)

      38
    • 3.3.5 System configuration for Ultra DMA

      38
  • 3.4 Jumper Settings

    41
    • 3.4.1 Location of setting jumpers

      41
    • 3.4.2 Factory default setting

      42
    • 3.4.3 Jumper configuration

      42
• CHAPTER 4 THEORY OF DEVICE OPERATION

  46
  • 4.1 Outline

    46
  • 4.2 Subassemblies

    46
    • 4.2.1 Disk

      46
    • 4.2.2 Head

      47
    • 4.2.3 Spindle

      47
    • 4.2.4 Actuator

      47
    • 4.2.5 Air filter

      48
  • 4.3 Circuit Configuration

    49
  • 4.4 Power-on Sequence

    51
  • 4.5 Self-calibration

    53
    • 4.5.1 Self-calibration contents

      53
    • 4.5.2 Execution timing of self-calibration

      54
    • 4.5.3 Command processing during self-calibration

      54
  • 4.6 Read/write Circuit

    55
    • 4.6.1 Read/write preamplifier (PreAMP)

      55
    • 4.6.2 Write circuit

      55
    • 4.6.3 Read circuit

      56
    • 4.6.4 Synthesizer circuit

      57
  • 4.7 Servo Control

    57
    • 4.7.1 Servo control circuit

      58
    • 4.7.2 Data-surface servo format

      61
    • 4.7.3 Servo frame format

      61
    • 4.7.4 Actuator motor control

      63
    • 4.7.5 Spindle motor control

      64
• CHAPTER 5 INTERFACE

  66
  • 5.1 Physical Interface

    67
    • 5.1.1 Interface signals

      67
    • 5.1.2 Signal assignment on the connector

      68
  • 5.2 Logical Interface

    71
    • 5.2.1 I/O registers

      71
    • 5.2.2 Command block registers

      73
    • 5.2.3 Control block registers

      78
  • 5.3 Host Commands

    78
    • 5.3.1 Command code and parameters

      79
    • 5.3.2 Command descriptions

      81
    • 5.3.3 Error posting

      131
  • 5.4 Command Protocol

    132
    • 5.4.1 Data transferring commands from device to host

      132
    • 5.4.2 Data transferring commands from host to device

      134
    • 5.4.3 Commands without data transfer

      136
    • 5.4.4 Other commands

      137
    • 5.4.5 DMA data transfer commands

      137
  • 5.5 Ultra DMA feature set

    139
    • 5.5.1 Overview

      139
    • 5.5.2 Phases of operation

      140
    • 5.5.3 Ultra DMA data in commands

      140
      • 5.5.3.1 Initiating an Ultra DMA data in burst

        140
      • 5.5.3.2 The data in transfer

        141
      • 5.5.3.3 Pausing an Ultra DMA data in burst

        141
      • 5.5.3.4 Terminating an Ultra DMA data in burst

        142
    • 5.5.4 Ultra DMA data out commands

      144
      • 5.5.4.1 Initiating an Ultra DMA data out burst

        144
      • 5.5.4.2 The data out transfer

        145
      • 5.5.4.3 Pausing an Ultra DMA data out burst

        145
      • 5.5.4.4 Terminating an Ultra DMA data out burst

        146
    • 5.5.5 Ultra DMA CRC rules

      148
    • 5.5.6 Series termination required for Ultra DMA

      149
  • 5.6 Timing

    150
    • 5.6.1 PIO data transfer

      150
    • 5.6.2 Multiword data transfer

      151
    • 5.6.3 Ultra DMA data transfer

      152
      • 5.6.3.1 Initiating an Ultra DMA data in burst

        152
      • 5.6.3.2 Ultra DMA data burst timing requirements

        153
      • 5.6.3.3 Sustained Ultra DMA data in burst

        155
      • 5.6.3.4 Host pausing an Ultra DMA data in burst

        156
      • 5.6.3.5 Device terminating an Ultra DMA data in burst

        157
      • 5.6.3.6 Host terminating an Ultra DMA data in burst

        158
      • 5.6.3.7 Initiating an Ultra DMA data out burst

        159
      • 5.6.3.8 Sustained Ultra DMA data out burst

        160
      • 5.6.3.9 Device pausing an Ultra DMA data out burst

        161
      • 5.6.3.10 Host terminating an Ultra DMA data out burst

        162
      • 5.6.3.11 Device terminating an Ultra DMA data in burst

        163
    • 5.6.4 Power-on and reset

      164
• CHAPTER 6 OPERATIONS

  166
  • 6.1 Device Response to the Reset

    166
    • 6.1.1 Response to power-on

      167
    • 6.1.2 Response to hardware reset

      168
    • 6.1.3 Response to software reset

      169
    • 6.1.4 Response to diagnostic command

      170
  • 6.2 Address Translation

    171
    • 6.2.1 Default parameters

      171
    • 6.2.2 Logical address

      172
  • 6.3 Power Save

    173
    • 6.3.1 Power save mode

      173
    • 6.3.2 Power commands

      175
  • 6.4 Defect Management

    175
    • 6.4.1 Spare area

      176
    • 6.4.2 Alternating defective sectors

      176
  • 6.5 Read-Ahead Cache

    178
    • 6.5.1 Data buffer configuration

      178
    • 6.5.2 Caching operation

      179
    • 6.5.3 Usage of read segment

      180
  • 6.6 Write Cache

    185
• Addresses

  187
• Reader Comment Form

  188
• back

  189